AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 73

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

<1:0>: Number of AGC Average Samples. This defines the
number of samples to be averaged before they are sent to the
CIC decimating filter (see Table 43).
Table 43. Number of AGC Average Samples
AGC Average Samples <1:0>
00
01
10
11
AGC Pole Location <7:0>
This 8-bit register is used to define the open-loop filter pole
location P. Its value can be set from 0 to 0.996 in steps of 0.0039.
This value of P is updated in the AGC loop each time the AGC
is initialized. This open-loop pole location directly impacts the
closed-loop pole locations, see the Automatic Gain Control
section.
AGC Desired Level <7:0>
This register contains the desired signal level or desired clipping
level, depending on operational mode. This desired request
level (R) can be set in dB from 0 to 23.99 in steps of 0.094 dB.
The request level (R) in dB should be converted to a register
setting by
AGC Loop Gain2 <7:0>
This 8-bit register is used to define the second possible open-
loop gain, K
0.0039. This value of K
initialized. When the magnitude-of-error signal in the loop is
greater than the AGC error threshold, then K
loop. K
AGC Loop Gain1 <7:0>
This 8-bit register is used to define the open-loop gain K
value can be set from 0 to 0.996 in steps of 0.0039. This value of
K is updated in the AGC loop each time the AGC is initialized.
When the magnitude-of-error signal in the loop is less than the
AGC error threshold, then K
only when the AGC is initialized.
I Path Signature Register <15:0>
This 16-bit signature register is for the I path of the channel
logic. The signature register records data on the networks that
leave the channel logic just before entering the second data
router.
Register Value = round
2
is updated only when the AGC is initialized.
2
. Its value can be set from 0 to 0.996 in steps of
2
is updated each time the AGC is
⎡
⎢
⎣
1
20
is used by the loop. K
log
R
Number of Samples Taken
1
2
3
4
10
(
) 2
× 64
2
⎤
⎥
⎦
is used by the
1
is updated
1
. Its
Rev. A | Page 73 of 80
Q Path Signature Register <15:0>
This 16-bit signature register is for the Q path of the channel
logic. The signature register records data on the networks that
leave the channel logic just before entering the second data
router.
BIST Control <15:0>
<15>: Disable Signature Generation Bit. When this bit is active
high, the signature registers do not produce a pseudorandom
output value, but instead directly load the 24-bit input data.
When this bit is cleared, the signature register produces a
pseudorandom output for every clock cycle that it is active. See
the User-Configurable, Built-In Self-Test (BIST) section for
details.
<14:0>: BIST Timer Bits. The <14:0> bits of this register form a
15-bit word that is loaded into the BIST timer. After loading the
BIST timer, the signature register is enabled for operation while
the timer is actively counting down. (See the User-
Configurable, Built-In Self-Test (BIST) section.)
OUTPUT PORT REGISTER MAP
This part of the memory map deals with the output data and
controls for parallel output ports.
Parallel Port Output Control <23:0>
<23>: Port C Append RSSI Bit. When this bit is set, an RSSI
word is appended to every I/Q output sample, irrespective of
whether the RSSI word is updated in the AGC. When this bit is
cleared, an RSSI word is appended to an I/Q output sample only
when the RSSI word is updated. The RSSI word is not output for
subsequent I/Q samples until the next time the RSSI is updated
in the AGC.
<22>: Port C, Data Format Bit. When this bit is set, the port is
configured for 8-bit parallel I/Q mode. When cleared, the port
is configured for 16-bit interleaved I/Q mode. See the Parallel
Port Output section for details.
<21>: Port C, AGC5 Enable Bit. When this bit is set, AGC5 data
(I/Q data) is output on parallel Output Port C (data bus). When
this bit is cleared, AGC5 data does not appear on Output
Port C.
<20>: Port C, AGC4 Enable Bit. Similar to Bit <21> for AGC4.
<19>: Port C, AGC3 Enable Bit. Similar to Bit <21> for AGC3.
<18>: Port C, AGC2 Enable Bit. Similar to Bit <21> for AGC2.
<17>: Port C, AGC1 Enable Bit. Similar to Bit <21> for AGC1.
<16>: Port C, AGC0 Enable Bit. Similar to Bit <21> for AGC0.
AD6636