AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 67

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

<0>: Port CD DC Correction Enable Bit. When the dc
correction enable bit is set, the dc offset correction function of
the I/Q correction block for the AB port is enabled. When
cleared, the dc offset correction value is given by the value of
the AB offset correction registers. If the Port A complex data
active bit of the ADC input control register is cleared (real input
mode), this bit is a don’t care.
Port AB, DC Offset Correction I <15:0>
This register holds the in-phase signal dc offset correction value
for complex data stream when dc correction is enabled. This
value should be set manually when automatic correction is
disabled. This 16-bit value is subtracted from the 16-bit ADC
Port A data (in-phase signal). This data is a don’t care in real
input mode.
Port AB, DC Offset Correction Q <15:0>
This register holds the quadrature phase signal dc offset
correction value for complex data stream when dc correction is
enabled. This value should be set manually when automatic
correction is disabled. This 16-bit value is subtracted from the
16-bit ADC Port B data (quadrature phase signal). This data is a
don’t care in real input mode.
Port CD, DC Offset Correction I <15:0>
This register holds the in-phase signal dc offset correction value
for complex data stream when dc correction is enabled. This
value should be set manually when automatic correction is
disabled. This 16-bit value is subtracted from the 16-bit ADC
Port C data (in-phase signal). This data is a don’t care in real
input mode.
Port CD, DC Offset Correction Q <15:0>
This register holds the quadrature phase signal dc offset
correction value for complex data stream when dc correction is
enabled. This value should be set manually when automatic
correction is disabled. This 16-bit value is subtracted from the
16-bit ADC Port D data (quadrature phase signal). This data is
a don’t care in real input mode.
Port AB, Phase Offset Correction <15:0>
This register holds the phase offset correction value for complex
data stream when the AB port phase correction is enabled. This
value is set manually when automatic correction is disabled.
This value is calculated as tan(phase_mismatch), where
phase_mismatch is the mismatch in phase between I (in-phase
signal) and Q (quadrature phase signal). This 14-bit value is
multiplied with 16-bit Q (quadrature phase signal, Input Port B)
and added to 16-bit I (in-phase signal, Input Port A). This data
is a don’t care in real input mode.
Port AB, Amplitude Offset Correction <15:0>
This register holds the amplitude offset correction value for
complex data stream when the AB port amplitude correction is
Rev. A | Page 67 of 80
enabled. This value is set manually when automatic correction
is disabled. This value is calculated as (Mag(Q) − Mag(I)),
where I is the in-phase signal and Q is the quadrature phase
signal. This 14-bit value is multiplied with 16-bit Q (quadrature
phase signal, Input Port B) and added to 16-bit Q (quadrature
phase signal, Input Port B). This data is a don’t care in real
input mode.
Port CD, Phase Offset Correction <15:0>
This register holds the phase offset correction value for the
complex data stream when CD port phase correction is enabled.
This value should be set manually when automatic correction is
disabled. This value should be calculated as tangent
(phase_mismatch), where phase_mismatch is the mismatch in
phase between I (in-phase signal) and Q (quadrature phase
signal). This 14-bit value is multiplied with 16-bit Q
(quadrature phase signal, Input Port D) and added to 16-bit I
(in-phase signal, Input Port C). This data is a don’t care in real
input mode.
Port CD, Amplitude Offset Correction <15:0>
This register holds the amplitude offset correction value for
complex data stream when CD port amplitude correction is
enabled. This value is set manually when automatic correction
is disabled. This value is calculated as (Mag(Q) − Mag(I)),
where I is the in-phase signal and Q is the quadrature phase
signal. This 14-bit value is multiplied with 16-bit Q (quadrature
phase signal, Input Port D) and added to 16-bit Q (quadrature
phase signal, Input Port D). This data is a don’t care in real
input mode.
Port A Gain Control <7:0>
<7>: This bit is open.
<6:1>: This 6-bit word specifies the relinearization pipe delay to
be used in the ADC input gain control block. The decimal
representation of these bits is the number of input clock cycle
pipeline delays between the external EXP data output and the
internal application of relinearization based on EXP.
<0>: Gain Control Enable Bit. This bit controls the configura-
tion of the EXP<2:0> bits for Channel A. When the gain control
enable bit is Logic 1, the EXP<2:0> bits are configured as
outputs. When this bit is cleared, the EXP<2:0> bits are inputs.
Port A Dwell Timer <19:0>
This register is used to set the dwell time for the gain control
block. When gain control block is active and detects a decrease
in the signal level below the lower threshold value (program-
mable), a dwell time counter is initiated to provide temporal
hysteresis. Doing so prevents the gain from being switched
continuously. Note that the dwell timer is turned on after a drop
below the lower threshold is detected in the signal level only.
AD6636