AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 70

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
MRCF Control Register <12:0>
<12:10>: MRCF Data Select Bits. These bits are used to select
the input source for the MRCF filter. Each MRCF filter can be
driven by output from the HB2 filter of any channel independ-
ently. Table 37 shows the available selections.
Table 37. MRCF Data Select Bits
MRCF Data Select<2:0>
000
001
010
011
1x0
1x1
<9>: Interpolating Half-Band Enable Bit. When this bit is set,
the interpolating half-band filter, driven by the output of the
CRCF block, is enabled. When cleared, the interpolating half-
band filter is bypassed and its output is the same as its input.
The interpolating half-band filter doubles the data rate.
<8>: This bit is open.
<7>: Half-Rate Bit. When this bit is set, the MRCF filter
operates using half the PLL clock rate. This is used for power
savings when there is sufficient time to complete MRCF
filtering using only half the PLL clock rate. When this bit is
cleared, the MRCF filter operates at the full PLL clock rate. (See
the MonoRate RAM Coefficient Filter section.)
<6:4>: MRCF Number of Taps Bits. This 3-bit word should be
written with one less than the number of taps that are calculated
by the MRCF filter. The filter length is given by the decimal
value of this register plus 1. A value of 0 represents a 1-tap filter
and maximum value of 7 represents an 8-tap filter.
<3:2>: MRCF Scale Factor Bits. The output of the MRCF filter is
scaled according to the value of these bits. Table 38 describes
the attenuation corresponding to each setting.
Table 38. MRCF Scale Factor
MRCF Scale<1:0>
00
01
10
11
<1>: This bit is open.
<0>: MRCF Bypass Bit. When this bit is set, the MRCF filter is
bypassed and, therefore, the output of the MRCF is the same as
its input. When this bit is cleared, the MRCF has normal
operation as programmed by its control register.
Scale Factor
18.06 dB attenuation (left-shift 3 bits)
12.04 dB attenuation (left-shift 2 bits)
6.02 dB attenuation (left-shift 1 bit)
No scaling (0 dB)
MRCF Input Source
MRCF input taken from Channel 0
MRCF input taken from Channel 1
MRCF input taken from Channel 2
MRCF input taken from Channel 3
MRCF input taken from Channel 4
MRCF input taken from Channel 5
Rev. A | Page 70 of 80
MRCF Coefficient Memory
The MRCF coefficient memory consists of eight coefficients,
each six bits wide. The memory extends from Address 0x80 to
Address 0x87. The coefficients should be written in twos
complement format.
DRCF Control Register <11:0>
<11>: DRCF Bypass Bit. When this bit is set, the DRCF filter is
bypassed and, therefore, its output is the same as its input.
When this bit is cleared, the DRCF has normal operation as
programmed by the rest of this control register.
<10>: Symmetry Bit. When this bit is set, it indicates that the
DRCF is implementing a symmetrical filter and only half the
impulse response needs to be written into the DRCF coefficient
RAM. When this bit is cleared, the filter is asymmetrical and
complete impulse response of the filter should be written to the
coefficient RAM. When this filter is symmetrical, it can
implement up to 128 filter taps.
<9:8>: DRCF Multiply Accumulate Scale Bits. The output of the
DRCF filter is scaled according to the value of these bits.
Table 39 lists the attenuation corresponding to each setting.
Table 39. DRCF Multiply Accumulate Scale Bits
DRCF Scale<1:0>
00
01
10
11
<7:4>: DRCF Decimation Rate. This 4-bit word should be
written with one less than the decimation rate of the DRCF
filter. A value of 0 represents a decimation rate of 1 (no rate
change), and the maximum value of 15 represents a decimation
of 16. Filtering can be implemented irrespective of the
decimation rate.
<3:0>: DRCF Decimation Phase Bits. This 4-bit word represents
the decimation phase used by the DRCF filter. The valid range
is 0 up to M
DRCF filter. This word is primarily used for synchronization of
multiple channels of the AD6636, when more than one channel
is used for filtering one signal (one carrier).
DRCF Coefficient Offset <7:0>
This register is used to specify which section of the 64-word
coefficient memory is used for a filter. It can be used to select
between multiple filters that are loaded into memory and
referenced by this pointer. This register is shadowed, and the
filter pointer is updated every time a new filter is started. This
allows the coefficient offset to be written even while a filter is
being computed without disturbing operation. The next sample
comes out of the DRCF with the new filter.
DRCF
− 1, where M
Scale Factor
18.06 dB attenuation (left-shift 3 bits)
12.04 dB attenuation (left-shift 2 bits)
6.02 dB attenuation (left-shift 1 bit)
No scaling (0 dB)
DRCF
is the decimation rate of the