AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 39

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

The interleaving function is a simple time-multiplexing
function, with a lower data rate on the input side and a higher
data rate on the output side. The output data rate is the sum of
all input stream data rates that are combined.
The channels that need to be combined are programmable with
sufficient flexibility. Table 23 gives the combinations that are
possible using a 4-bit word (stream control bits) in the Parallel
Port Control 2 register.
After interleaving of data (see the Output Data Router section),
the data is passed to the second subblock, in which either
complex filter completion or biphase filtering can be performed.
Complex Filter Completion
In normal operation, each individual channel’s filter performs
real coefficient, complex data filtering.
Two channels are used to perform complex coefficient data
filtering. One channel is loaded with the real part (in-phase) of
the coefficients; the other channel is loaded with the imaginary
part (quadrature) of the coefficients.
Table 23. Stream Control Bit Combinations
Stream Control Bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Any other state
Output Streams
Ch 0/Ch 1 combined, Ch 2, Ch 3, Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2 combined, Ch 3, Ch 4, Ch5 independent
Ch 0/Ch 1/Ch 2/Ch 3 combined; Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3/Ch 4 combined; Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3/Ch 4/Ch 5 combined
Ch 0/Ch 1/Ch 2 combined, Ch 3/Ch 4/Ch 5 combined
Ch 0/Ch 1 combined, Ch 2/Ch 3 combined, Ch 4/Ch 5 combined
Ch 0/Ch 1 combined, Ch 2/Ch 3 combined, Ch 4, Ch 5 independent
Ch 0/Ch 1/Ch 2 combined, Ch 3/Ch 4 combined, Ch 5 independent
Ch 0/Ch 1/Ch 2/Ch 3 combined, Ch 4/Ch 5 combined.
Independent channels
CH0
CH1
CH2
CH3
CH4
CH5
CONTROL
STREAM
Figure 38. Output Data Router Block Diagram
STR0
STR1
STR2
STR3
STR4
STR5
COMPLETION
COMPLEX
FILTER
Rev. A | Page 39 of 80
AGC0
AGC1
AGC2
AGC3
AGC4
AGC5
AGC0
AGC1
AGC2
AGC3
AGC4
AGC5
The calculated terms include:
•
•
Using these terms, the complex filter is completed by applying
The channels to be combined can be programmed using a 3-bit
complex control word in the Parallel Output Control 2 register.
The values for the 3-bit control word and the corresponding
settings are listed in Table 24.
These outputs go to the six available AGCs. Not all AGCs need
to be used in the different applications, so unused AGCs can be
bypassed and the output data streams ignored by the parallel
output ports. For example, if Stream 0 and Stream 1 are
combined for a complex filter, AGC1 can be bypassed, because
Stream 1 is already combined into Stream 0 and sent to AGC0.
(ICi, QCi) from first channel
(Icq, QCq) from the second channel
(I + jQ) (Ci + jCq) = (ICi − QCq) + j(ICq + QCi)
PARALLEL
PARALLEL
PARALLEL
PORT A
PORT B
PORT C
No. of Streams
4
3
2
1
2
3
3
3
2
6
5
AD6636