AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 48

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
USER-CONFIGURABLE, BUILT-IN SELF-TEST (BIST)
Each channel of AD6636 includes a BIST block. The BIST,
along with an internal test signal (pseudorandom test input
signal), can be used to generate a signature. This signature can
be compared with a known good device and an untested device
to see if the untested device is functional.
BIST timer bits in the BIST control register can be programmed
with a timer value that determines the number of clock cycles
that the output of the channels (output of AGC) have
accumulated. When the disable signature generation bit is
written with Logic 0, the BIST timer is counted down and a
signature register is written with the accumulated output of the
AD6636 channel.
When the BIST timer expires, the signature register for I and Q
paths can be read back to compare it with the signature register
from a known good device.
CHIP SYNCHRONIZATION
The AD6636 offers two types of synchronization: start sync and
hop sync. Start sync is used to bring individual channels out of
sleep after programming. It can also be used while AD6636 is
operational to resynchronize the internal clocks. Hop sync is
used to change or update the NCO frequency tuning word and
the NCO phase offset word.
Two methods can be used to initiate a start sync or hop sync:
•
•
The pin synchronization configuration register (Address 0x04)
is used to make pin synchronization even more flexible. The
part can be programmed to be edge-sensitive or level-sensitive
for SYNC pins. In edge-sensitive mode, a rising edge on the
SYNC pins is recognized as a synchronization event.
Start
Start refers to the startup of an individual channel or chip, or of
multiple chips. If a channel is not used, it should be put into
sleep mode to reduce power dissipation. Following a hard reset
(low pulse on the RESET pin), all channels are placed into sleep
mode. Alternatively, channels can be put to sleep manually by
writing 0 to the sleep register.
Soft sync is provided by the memory map registers and is
applied to channels directly through the microport or serial
port interface.
Pin sync is provided using four hard-wired SYNC[3:0] pins.
Each channel is programmed to listen to one of these SYNC
pins and do a start sync or a hop sync when a signal is
received on these pins.
Rev. A | Page 48 of 80
Start with Soft Sync
The AD6636 can synchronize channels or chips under micro-
processor control. The start hold-off counter, in conjunction
with the soft start enable bit and the channel enable bits, enables
this synchronization.
To synchronize the start of multiple channels via micro-
processor control:
1.
2.
3.
4.
Note that when using SPI or SPORT for programming these
registers, the last step in the above procedure needs to be
repeated. Therefore, the soft synchronization configuration
register is written twice.
Start with Pin Sync
Four sync pins (0, 1, 2, and 3) provide very accurate synchro-
nization among channels. Each channel can be programmed to
monitor any of the four sync pins.
To start the channels with a pin sync:
1.
2.
3.
4.
Hop
Hop is a jump from one NCO frequency and/or phase offset to
a new NCO frequency and/or phase offset. This change in
frequency and/or phase offset can be synchronized via
microprocessor control (soft sync) or via an external sync signal
(pin sync).
Write the channel enable register to enable one or more
channels, if the channels are inactive.
Write the NCO start hold-off counter register(s) with the
appropriate value (greater than 0 and less than 2
Write 0x00 to the soft synchronization configuration
register.
Write the soft sync channel enable bit(s) and soft start
synchronization enable bit high in the soft synchronization
configuration register. This starts the countdown by the
start hold-off counter. When the count reaches 1, the
channels are activated or resynchronized.
Write the channel register to enable one more channels, if
the channels are inactive.
Write the NCO start hold-off counter register(s) with the
appropriate value (greater than 0 and less than 2
Program the channel NCO control registers to monitor the
appropriate SYNC pins.
Write the start synchronization enable bit and SYNC pin
enable bits high in the pin synchronization configuration
register. This starts the countdown of the start hold-off
counter. When the count reaches 1, the channels are
activated or resynchronized.
16
16
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