AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 2

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
TABLE OF CONTENTS
General Description ......................................................................... 4
Specifications..................................................................................... 6
Absolute Maximum Ratings.......................................................... 10
Pin Configuration and Function Descriptions........................... 11
Timing Diagrams............................................................................ 14
Theory of Operation ...................................................................... 20
Recommended Operating Conditions ...................................... 6
Electrical Characteristics............................................................. 6
General Timing Characteristics
Microport Timing Characteristics
Serial Port Timing Characteristics
Explanation of Test Levels for Specifications............................ 9
Thermal Characteristics ............................................................ 10
ESD Caution................................................................................ 10
Pin Listing for Power, Ground, Data, and Address Buses..... 13
ADC Input Port .......................................................................... 20
PLL Clock Multiplier ................................................................. 21
ADC Gain Control ..................................................................... 22
ADC Input Port Monitor Function.......................................... 23
Quadrature I/Q Correction Block............................................ 25
Input Crossbar Matrix ............................................................... 27
Numerically Controlled Oscillator (NCO) ............................. 27
Fifth-Order CIC Filter ............................................................... 29
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Rev. A | Page 2 of 80
Memory Map .................................................................................. 60
Design Notes ................................................................................... 77
Outline Dimensions ....................................................................... 79
FIR Half-Band Block.................................................................. 30
Intermediate Data Router ......................................................... 33
MonoRate RAM Coefficient Filter (MRCF)........................... 33
Decimating RAM Coefficient Filter (DRCF) ......................... 34
Channel RAM Coefficient Filter (CRCF) ............................... 36
Interpolating Half-Band Filter.................................................. 38
Output Data Router ................................................................... 38
Automatic Gain Control............................................................ 40
Parallel Port Output ................................................................... 44
User-Configurable, Built-In Self-Test (BIST)......................... 48
Chip Synchronization ................................................................ 48
Serial Port Control ..................................................................... 49
Microport .................................................................................... 58
Reading the Memory Map Table.............................................. 60
Global Register Map .................................................................. 62
Input Port Register Map ............................................................ 65
Channel Register Map ............................................................... 68
Output Port Register Map ......................................................... 73
Ordering Guide .......................................................................... 79