AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 9

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

SERIAL PORT TIMING CHARACTERISTICS
Table 5.
Parameter
SERIAL PORT CLOCK TIMING REQUIREMENTS
SPI PORT CONTROL TIMING REQUIREMENTS (MODE = 0)
SPORT MODE CONTROL TIMING REQUIREMENTS (MODE = 1)
1
2
3
EXPLANATION OF TEST LEVELS FOR SPECIFICATIONS
Table 6.
Test Level
I
II
III
IV
V
VI
All timing specifications are valid over the VDDCORE range of 1.7 V to 1.9 V and the VDDIO range of 3.0 V to 3.6 V.
C
SCLK rise/fall time should be 3 ns maximum.
LOAD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCLK
SCLKL
SCLKH
SSDI
HSDI
SSCS
HSCS
DSDO
SSDI
HSDI
SSRFS
HSRFS
SSTFS
HSTFS
SSCS
HSCS
DSDO
= 40 pF on all outputs, unless otherwise noted.
SCLK Period
SCLK Low Time
SCLK High Time
SDI to ↑SCLK Setup Time
SDI to ↑SCLK Hold Time
SCS to ↑SCLK Setup Time
SCS to ↑SCLK Hold Time
↑SCLK to SDO Delay Time
SDI to ↑SCLK Setup Time
SDI to ↑SCLK Hold Time
SRFS to ↓SCLK Setup Time
SRFS to ↓SCLK Hold Time
STFS to ↓SCLK Setup Time
STFS to ↑SCLK Hold Time
SCS to ↑SCLK Setup Time
SCS to ↑SCLK Hold Time
↑SCLK to SDO Delay Time
Description
100% production tested.
100% production tested at 25°C, and sample tested at specified temperatures.
Sample tested only.
Parameter guaranteed by design and analysis.
Parameter is typical value only.
100% production tested at 25°C, and sampled tested at temperature extremes.
1, , 2 3
Rev. A | Page 9 of 80
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
IV
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Min
10.0
1.60
1.60
1.30
0.40
4.12
−2.78
4.28
0.80
0.40
1.60
−0.13
1.60
−0.30
4.12
−2.76
4.29
0.5 × t
Typ
0.5 × t
SCLK
SCLK
Max
7.96
7.95
AD6636
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit