AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 63

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

Note that if the access bits are set for more than one channel
during write access, all channels with access are written with the
same data. This is especially useful when more than one
channel has similar configurations. During a read operation, if
more than one channel has access, the read access is given to the
channel with the lowest channel number. For example, if both
Channel 4 and Channel 2 have access bits set, then read access
is given to Channel 2.
Channel Enable Register <5:0>
<5>: Channel 5 Enable Bit. When this bit is set, Channel 5 logic
is enabled. When this bit is cleared, Channel 5 is disabled and
the channel’s logic does not consume any power. On power-up,
this bit comes up with Logic 0 and the channel is disabled. A
start sync does not start Channel 5 unless this bit is set before
issuing the start sync.
<4>: Channel 4 Enable Bit. Similar to Bit <5> for Channel 4.
<3>: Channel 3 Enable Bit. Similar to Bit <5> for Channel 3.
<2>: Channel 2 Enable Bit. Similar to Bit <5> for Channel 2.
<1>: Channel 1 Enable Bit. Similar to Bit <5> for Channel 1.
<0>: Channel 0 Enable Bit. Similar to Bit <5> for Channel 0.
Pin Synchronization Configuration <7:0>
<7>: Hop Synchronization Enable Bit. This bit is a global enable
for any hop synchronization involving SYNC pins. When this
bit is set, hop synchronization is enabled for all channels that
are programmed for pin synchronization. When this bit is
cleared, hop synchronization is not performed for any channel
that is programmed for pin synchronization.
<6>: Start Synchronization Enable Bit. This bit is a global enable
for any start synchronization involving SYNC pins. When this
bit is set, start synchronization is enabled for all channels that
are programmed for pin synchronization. When this bit is
cleared, start synchronization is not performed for any channel
that is programmed for pin synchronization.
<5>: First Sync Only Bit. When this bit is set, the NCO
synchronization logic only recognizes the first synchronization
event as valid. All other requests for synchronization events are
ignored as long as this bit is set. When cleared, all synchro-
nization events are acted upon.
<4>: Edge-Sensitivity Bit. When this bit is set, the rising edge on
the SYNC pin(s) is detected as a synchronization event (edge-
sensitive detection). When cleared, Logic 1 on the SYNC pin(s)
is detected as a synchronization event (level-sensitive
detection).
<3>: Enable Synchronization from SYNC3 Bit. When this bit is
set, the SYNC3 pin can be used for synchronization. When this
bit is cleared, the SYNC3 pin is ignored. This is a global enable
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for all SYNC pins, and each individual channel selects which
pin it listens to.
<2>: Enable Synchronization from SYNC2 Bit. Similar to
Bit <3> for the SYNC[2] pin.
<1>: Enable Synchronization from SYNC1 Bit. Similar to
Bit <3> for the SYNC1 pin.
<0>: Enable Synchronization from SYNC0 bit. Similar to
Bit <3> for the SYNC0 pin.
Soft Synchronization Configuration <7:0>
<7>: Soft Hop Synchronization Enable Bit. When this bit is set,
hop synchronization is enabled for all channels selected using
Bits 5:0. When this bit is cleared, hop synchronization is not
performed for any channels selected using Bits 5:0.
<6>: Soft Start Synchronization Enable Bit. When this bit is set,
start synchronization is enabled for all channels selected using
Bits 5:0. When this bit is cleared, start synchronization is not
performed for any channels selected using Bits 5:0.
Bits<5:0> form the SOFT_SYNC control bits. These bits can be
written to by the controller to initiate the synchronization of a
selected channel.
<5>: Soft Sync Channel 5 Enable Bit. When this bit is set, it
enables Channel 5 to receive a hop sync or start sync, as defined
by Bit 7 and Bit 6, respectively. When cleared, Channel 5 does
not receive any soft sync.
<4>: Soft Sync Channel 4 Enable Bit. Similar to Bit <5> for
Channel 4.
<3>: Soft Sync Channel 3 Enable Bit. Similar to Bit <5> for
Channel 3.
<2>: Soft Sync Channel 2 Enable Bit. Similar to Bit <5> for
Channel 2.
<1>: Soft Sync Channel 1 Enable Bit. Similar to Bit <5> for
Channel 1.
<0>: Soft Sync Channel 0 Enable Bit. Similar to Bit <5> for
Channel 0.
LVDS Control Register <10:0>
<10>: CMOS Mode Bit. When this bit is set, the ADC ports
operate in CMOS mode. When this bit is cleared, the ADC
ports operate in LVDS mode. The default is Logic 1 or CMOS
mode. In LVDS mode, two CMOS ADC port pins are used to
form one differential pair of LVDS ADC ports.
<9>: Reserved. This bit should always be written as Logic 1.
<8>: Autocalibrate Enable Bit. When this bit is set, the auto-
calibration cycle is invoked for the LVDS pads. At the end of
calibration, this calibration value is set for the LVDS pads.
AD6636