AD6636CBCZ Analog Devices Inc, AD6636CBCZ Datasheet - Page 4

• Manufacturer Part Number: AD6636CBCZ
• Description: IC DIGITAL DWNCONV 4CH 256CSPBGA
• Manufacturer: Analog Devices Inc
• Series: AD6636r

Specifications of AD6636CBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Secondary Attributes: Down Converter
• Current - Supply: 450mA
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 256-CSPBGA
• Brief Features: 4/6 Independent Wideband Processing Channel, Quadrature Correction & DC Correction For Complex Input
• Supply Voltage Range: 1.7V To 1.9V
• Operating Temperature Range: -40°C To +85°C
• Ic Function: Digital Down Converter (DDC)
• Rohs Compliant: Yes
• Pin Count: 256
• Screening Level: Industrial
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Frequency: -
• Gain: -
• Noise Figure: -
• Lead Free Status / Rohs Status: Compliant

AD6636
GENERAL DESCRIPTION
The AD6636 is a digital downconverter intended for IF
sampling or oversampled baseband radios requiring wide
bandwidth input signals. The AD6636 has been optimized for
the demanding filtering requirements of wideband standards,
such as CDMA2000, UMTS, and TD-SCDMA, but is flexible
enough to support wider standards such as WiMAX. The
AD6636 is designed for radio systems that use either an IF
sampling ADC or a baseband sampling ADC.
The AD6636 channels have the following signal processing
stages: a frequency translator, a fifth-order cascaded integrated
comb filter, two sets of cascaded fixed-coefficient FIR and half-
band filters, three cascaded programmable coefficient sum-of-
product FIR filters, an interpolating half-band filter (IHB), and
a digital automatic gain control (AGC) block. Multiple modes
are supported for clocking data into and out of the chip and
provide flexibility for interfacing to a wide variety of digitizers.
Programming and control are accomplished via serial or
microport interfaces.
Input ports can take input data at up to 150 MSPS. Up to
300 MSPS input data can be supported using two input ports
(some external interface logic is required) and two internal
channels processing in tandem. Biphase filtering in the output
data router is selected to complete the combined filtering mode.
The four input ports can operate in CMOS mode, or two ports
can be combined for LVDS input mode. The maximum input
data rate for each input port is 150 MHz.
Frequency translation is accomplished with a 32-bit complex
numerically controlled oscillator (NCO). It has greater than
110 dBc SFDR. This stage translates either a real or complex
input signal from intermediate frequency (IF) to a baseband
complex digital output. Phase and amplitude dither can be
enabled on-chip to improve spurious performance of the NCO.
A 16-bit phase-offset word is available to create a known phase
relationship between multiple AD6636 chips or channels. The
NCO can also be bypassed so that baseband I and Q inputs can
be provided directly from baseband sampling ADCs through
input ports.
Following frequency translation is a fifth-order CIC filter with a
programmable decimation between 1 and 32. This filter is used
to lower the sample rate efficiently, while providing sufficient
alias rejection at frequencies with higher frequency offsets from
the signal of interest.
Following the CIC5 are two sets of filters. Each set has a non-
decimating FIR filter and a decimate-by-2 half-band filter. The
FIR1 filter provides about 30 dB of rejection, while the HB1
filter provides about 77 dB of rejection. They can be used
together to achieve a 107 dB stop band alias rejection, or they
can be individually bypassed to save power. The FIR2 filter
provides about 30 dB of rejection, while the HB2 filter provides
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about 65 dB of rejection. The filters can be used either together
to achieve more than 95 dB stop band alias rejection, or can be
individually bypassed to save power. FIR1 and HB1 filters can
run with a maximum input rate of 150 MSPS. In contrast, FIR2
and HB2 can run with a maximum input rate of 75 MSPS (input
rate to FIR2 and HB2 filters).
The programmable filtering is divided into three cascaded RAM
coefficient filters (RCFs) for flexible and power efficient
filtering. The first filter in the cascade is the MRCF, consisting
of a programmable nondecimating FIR. It is followed by
programmable FIR filters (DRCF) with decimation from 1 to
16. They can be used either together to provide high rejection
filters, or independently to save power. The maximum input
rate to the MRCF is one-fourth of the PLL clock rate.
The channel RCF (CRCF) is the last programmable FIR filter
with programmable decimation from 1 to 16. It typically is used
to meet the spectral mask requirements for the air standard of
interest. This could be an RRC, antialiasing filter or any other
real data filter. Decimation in preceding blocks is used to keep
the input rate of this stage as low as possible for the best filter
performance.
The last filter stage in the chain is an interpolate-by-2 half-band
filter, which is used to up-sample the CRCF output to produce
higher output oversampling. Signal rejection requirements for
this stage are relaxed because preceding filters have filtered the
blockers and adjacent carriers already.
Each input port of the AD6636 has its own clock used for
latching onto the input data, but the Input Port A clock (CLKA)
is also used as the input for an on-board PLL clock multiplier.
The output of the PLL clock is used for processing all filters and
processing blocks beyond the data router following the CIC
filter. The PLL clock can be programmed to have a maximum
clock rate of 200 MHz.
A data routing block (DR) is used to distribute data from the
CICs to the various channel filters. This block allows multiple
back-end filter chains to work together to process high
bandwidth signals or to make even sharper filter transitions
than a single channel can perform. It can also allow complex
filtering operations to be achieved in the programmable filters.
The digital AGC provides the user with scaled digital outputs
based on the rms level of the signal present at the output of the
digital filters. The user can set the requested level and time
constant of the AGC loop for optimum performance of the
postprocessor. This is a critical function in the base station for
CDMA applications where the power level must be well
controlled going into the RAKE receivers. It has programmable
clipping and rounding control to provide different output
resolutions.