XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
DCM Timing Parameters
All devices are 100% functionally tested. Because of the dif-
ficulty in directly measuring many internal timing parame-
ters, those parameters are derived from benchmark timing
patterns. The following guidelines reflect worst-case values
Operating Frequency Ranges
e
Table 54: Operating Frequency Ranges
Description
Output Clocks (Low Frequency Mode)
CLK0, CLK90, CLK180, CLK270
(5,6)
CLK2X, CLK2X180
CLKDV
CLKFX, CLKFX180
Input Clocks (Low Frequency Mode)
(1,3,4)
CLKIN (using DLL outputs)
(2,3,4)
CLKIN (using CLKFX outputs)
PSCLK
Output Clocks (High Frequency Mode)
(6)
CLK0, CLK180
CLKDV
CLKFX, CLKFX180
Input Clocks (High Frequency Mode)
(1,3,4,6)
CLKIN (using DLL outputs)
(2,3,4)
CLKIN (using CLKFX outputs)
PSCLK
Notes:
1. “DLL outputs” is used here to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. If both DLL and CLKFX outputs are used, follow the more restrictive specification.
3. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used, then double these values.
4. If the CLKIN_DIVIDE_BY_2 attribute of the DCM is used and CLKIN frequency > 400 MHz, CLKIN duty cycle must be within ±5%
(45/55 to 55/45).
5. CLK2X and CLK2X180 may not be used as the input to the CLKFB pin. See the
information.
6. For the XC2VP100 -6 device only, clock macros for corner DCMS (X0Y0, X5Y0, X0Y1, X5Y1) are required to operate at maximum
clock frequency. See
XAPP685
for implementation examples.
DS083 (v4.7) November 5, 2007
Product Specification
across the recommended operating conditions. All output
jitter and phase specifications are determined through sta-
tistical measurement at the package pins.
Symbol
Constraints
CLKOUT_FREQ_1X_LF_MIN
CLKOUT_FREQ_1X_LF_MAX
CLKOUT_FREQ_2X_LF_MIN
CLKOUT_FREQ_2X_LF_MAX
CLKOUT_FREQ_DV_LF_MIN
CLKOUT_FREQ_DV_LF_MAX
CLKOUT_FREQ_FX_LF_MIN
CLKOUT_FREQ_FX_LF_MAX
CLKIN_FREQ_DLL_LF_MIN
CLKIN_FREQ_DLL_LF_MAX
CLKIN_FREQ_FX_LF_MIN
CLKIN_FREQ_FX_LF_MAX
PSCLK_FREQ_LF_MIN
PSCLK_FREQ_LF_MAX
CLKOUT_FREQ_1X_HF_MIN
CLKOUT_FREQ_1X_HF_MAX
CLKOUT_FREQ_DV_HF_MIN
CLKOUT_FREQ_DV_HF_MAX
CLKOUT_FREQ_FX_HF_MIN
CLKOUT_FREQ_FX_HF_MAX
CLKIN_FREQ_DLL_HF_MIN
CLKIN_FREQ_DLL_HF_MAX
CLKIN_FREQ_FX_HF_MIN
CLKIN_FREQ_FX_HF_MAX
PSCLK_FREQ_HF_MIN
PSCLK_FREQ_HF_MAX
www.xilinx.com
Speed Grade
-7
-6
-5
24.00
24.00
24.00
270.00
210.00
180.00
48.00
48.00
48.00
450.00
420.00
360.00
1.50
1.50
1.50
140.00
140.00
120.00
24.00
24.00
24.00
240.00
240.00
210.00
24.00
24.00
24.00
270.00
210.00
180.00
1.00
1.00
1.00
240.00
240.00
210.00
0.01
0.01
0.01
450.00
420.00
360.00
48.00
48.00
48.00
450.00
420.00
360.00
3.00
3.00
3.00
280.00
280.00
240.00
210.00
210.00
210.00
320.00
320.00
270.00
48.00
48.00
48.00
450.00
420.00
360.00
50.00
50.00
50.00
320.00
320.00
270.00
0.01
0.01
0.01
450.00
420.00
360.00
Virtex-II Pro Platform FPGA User Guide
Module 3 of 4
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for more
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