XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
CLKIN
CLKOUT_PHASE_SHIFT
CLKFB
= NONE
CLKIN
CLKOUT_PHASE_SHIFT
CLKFB
= FIXED
CLKIN
CLKOUT_PHASE_SHIFT
= VARIABLE
CLKFB
Two separate components of the phase shift range must be
understood:
attribute range
PHASE_SHIFT
DCM timing parameter range
FINE_SHIFT_RANGE
The
attribute is the numerator in the following
PHASE_SHIFT
equation:
Phase Shift (ns) = (
PHASE_SHIFT
The full range of this attribute is always -255 to +255, but its
practical range varies with CLKIN frequency, as constrained
by the
component, which represents
FINE_SHIFT_RANGE
the total delay achievable by the phase shift delay line. Total
delay is a function of the number of delay taps used in the
circuit. Across process, voltage, and temperature, this abso-
lute range is guaranteed to be as specified under DCM Tim-
ing Parameters in
Virtex-II Pro and Virtex-II Pro X Platform
FPGAs: DC and Switching
Characteristics.
Absolute range (fixed mode) = ±
FINE_SHIFT_RANGE
Absolute range (variable mode) = ±
The reason for the difference between fixed and variable
modes is as follows. For variable mode to allow symmetric,
dynamic sweeps from -255/256 to +255/256, the DCM sets
the "zero phase skew" point as the middle of the delay line,
thus dividing the total delay line range in half. In fixed mode,
Table 30: DCM Frequency Ranges
Output Clock
CLKIN Input
CLK0, CLK180
CLKIN_FREQ_DLL_LF
CLK90, CLK270
CLKIN_FREQ_DLL_LF
CLK2X, CLK2X180
CLKIN_FREQ_DLL_LF
CLKDV
CLKIN_FREQ_DLL_LF
CLKFX, CLKFX180
CLKIN_FREQ_FX_LF
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
(PS/256) x PERIOD CLKIN
(PS negative)
(PS/256) x PERIOD CLKIN
(PS negative)
Figure 63: Fine-Phase Shifting Effects
since the
ration, the entire delay line is available for insertion into
either the CLKIN or CLKFB path (to create either positive or
negative skew).
Taking both of these components into consideration, the fol-
lowing are some usage examples:
If PERIOD
/256) * PERIOD
CLKIN
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT in
variable mode it is limited to
If PERIOD
PHASE_SHIFT
Operating Modes
The frequency ranges of DCM input and output clocks
depend
low-frequency mode or high-frequency mode, according to
/2
FINE_SHIFT_RANGE
Table
30. For actual values, see
Virtex-II Pro X Platform FPGAs: DC and Switching Charac-
teristics. The CLK2X, CLK2X180, CLK90, and CLK270 out-
puts are not available in high-frequency mode.
High or low-frequency mode is selected by an attribute.
Low-Frequency Mode
CLK Output
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_1X_LF
CLKOUT_FREQ_2X_LF
CLKOUT_FREQ_DV_LF
CLKOUT_FREQ_FX_LF
www.xilinx.com
(PS/256) x PERIOD CLKIN
(PS positive)
(PS/256) x PERIOD CLKIN
(PS positive)
DS031_48_110300
value never changes after configu-
PHASE_SHIFT
= 2 *
FINE_SHIFT_RANGE
CLKIN
fixed mode is limited to
±
64.
±
=
, then
FINE_SHIFT_RANGE
CLKIN
fixed mode is limited to
±
128.
±
≤ 0.5 *
FINE_SHIFT_RANGE
CLKIN
is limited to
255 in either mode.
±
on
the
operating
mode
specified,
Virtex-II Pro and
High-Frequency Mode
CLKIN Input
CLK Output
CLKIN_FREQ_DLL_HF
CLKOUT_FREQ_1X_HF
NA
NA
CLKIN_FREQ_DLL_HF
CLKOUT_FREQ_DV_HF
CLKIN_FREQ_FX_HF
CLKOUT_FREQ_FX_HF
, then
128, and in
255, and in
, then
either
NA
NA
Module 2 of 4
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