XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II Pro
source-synchronous transmitter and receiver data-valid windows.
Table 61: Duty Cycle Distortion and Clock-Tree Skew
Description
(1)
Duty Cycle Distortion
(2)
Clock Tree Skew
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by
asymmetrical rise/fall times.
T
applies to cases where the dedicated path from the DCM to the BUFG is bypassed and where local (IOB) inversion is
DCD_LOCAL
used to provide the negative-edge clock to the DDR element in the I/O. Users must follow the implementation guidelines contained
in
XAPP685
for these specifications to apply.
T
applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
DCD_CLK180
in the I/O.
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DS083 (v4.7) November 5, 2007
Product Specification
Symbol
Device
T
DCD_LOCAL
All
T
DCD_CLK180
T
XC2VP2
CKSKEW
XC2VP4
XC2VP7
XC2VP20
XC2VPX20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
www.xilinx.com
Speed Grade
7
6
5
0.10
0.10
0.20
0.10
0.11
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.13
0.20
0.21
0.22
0.20
0.21
0.22
0.20
0.22
0.24
0.33
0.34
0.35
0.40
0.41
0.42
0.54
0.59
0.64
0.54
0.59
0.64
N/A
0.79
0.87
Module 3 of 4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49