XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 129

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
3
0
R
2
DS083 (v4.7) November 5, 2007
This document provides Virtex™-II Pro Device/Package
Combinations, Maximum I/Os, and Virtex-II Pro Pin Defini-
tions, followed by pinout tables, for these packages:
FG256/FGG256 Fine-Pitch BGA Package
FG456/FGG456 Fine-Pitch BGA Package
FG676/FGG676 Fine-Pitch BGA Package
FF672 Flip-Chip Fine-Pitch BGA Package
FF896 Flip-Chip Fine-Pitch BGA Package
Virtex-II Pro Device/Package Combinations and Maximum I/Os
Wire-bond and flip-chip packages are available.
Table 2
show the maximum number of user I/Os possible in
wire-bond and flip-chip packages, respectively.
FG denotes wire-bond fine-pitch BGA
(1.00 mm pitch).
FGG denotes Pb-free wire-bond fine-pitch BGA
(1.00 mm pitch).
FF denotes flip-chip fine-pitch BGA
(1.00 mm pitch)
Table 2: Flip-Chip Packages Information
Package
FF672
Pitch (mm)
1.00
Size (mm)
27 x 27
Maximum I/Os
396
Table 3
shows the number of available I/Os, the number of RocketIO™ (or RocketIO X) multi-gigabit transceiver (MGT) pins,
and the number of differential I/O pairs for each Virtex-II Pro device/package combination. The number of I/Os per package
includes all user I/Os except the fifteen control pins (CCLK, DONE, M0, M1, M2, PROG_B, PWRDWN_B, TCK, TDI, TDO,
TMS, HSWAP_EN, DXN, DXP, and RSVD), the nine (per transceiver) RocketIO MGT pins (TXP, TXN, RXP, RXN,
AVCCAUXTX, AVCCAUXRX, VTTX, VTRX, and GNDA), and for Virtex-II Pro X devices only, the two BREFCLKN/
BREFCLKP differential clock input pairs (four pins). The Virtex-II Pro X devices are highlighted in bold type.
1. Unless otherwise noted, "Virtex-II Pro" refers to members of the Virtex-II Pro and/or Virtex-II Pro X families.
© 2002–2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is
a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs:
FF1152 Flip-Chip Fine-Pitch BGA Package
FF1148 Flip-Chip Fine-Pitch BGA Package
FF1517 Flip-Chip Fine-Pitch BGA Package
FF1704 Flip-Chip Fine-Pitch BGA Package
FF1696 Flip-Chip Fine-Pitch BGA Package
For device pinout diagrams and layout guidelines, refer to
the
Virtex-II Pro Platform FPGA User Guide
pinout files are also available for download from the Xilinx
website (
Table 1
and
.
Table 1: Wire-Bond Packages Information
Package
Pitch (mm)
Size (mm)
Maximum I/Os
Notes:
1. Wire-bond packages include FGGnnn Pb-free versions. See
Virtex-II Pro Ordering Examples (Module
FF896
FF1152
FF1148
1.00
1.00
1.00
31 x 31
35 x 35
35 x 35
556
644
812
www.xilinx.com
Pinout Information
Product Specification
. ASCII package
).
www.xilinx.com
(1)
FG256/
FG456/
(1)
FGG256
FGG456
1.00
1.00
17 x 17
23 x 23
140
248
1).
FF1517
FF1704
1.00
1.00
40 x 40
42.5 x 42.5
964
1040
FG676/
FGG676
1.00
26 x 26
412
FF1696
1.00
42.5 x 42.5
1200
Module 4 of 4
1

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