XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Table 11: LVCMOS Programmable Currents (Sink and Source)
SelectIO-Ultra
LVTTL
2 mA
LVCMOS33
2 mA
LVCMOS25
2 mA
LVCMOS18
2 mA
LVCMOS15
2 mA
Figure 23
shows the SSTL2, SSTL18, and HSTL configura-
tions. HSTL can sink current up to 48 mA. (HSTL IV)
V CCO
Clamp
OBUF
Diode
V REF
Figure 23: SSTL or HSTL SelectIO-Ultra Standards
All pads are protected against damage from electrostatic
discharge
(ESD)
and
from
over-voltage
Virtex-II Pro uses two memory cells to control the configura-
tion of an I/O as an input. This is to reduce the probability of
an I/O configured as an input from flipping to an output
when subjected to a single event upset (SEU) in space
applications.
Prior to configuration, all outputs not involved in configura-
tion are forced into their high-impedance state. The
pull-down resistors and the weak-keeper circuits are inac-
tive. The dedicated pin HSWAP_EN controls the pull-up
resistors prior to configuration. By default, HSWAP_EN is
set High, which disables the pull-up resistors on user I/O
pins. When HSWAP_EN is set Low, the pull-up resistors are
activated on user I/O pins.
All Virtex-II Pro IOBs (except RocketIO transceiver pins)
support IEEE 1149.1 and IEEE 1532 compatible Bound-
ary-Scan testing.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Programmable Current (Worst-Case Guaranteed Minimum)
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
Input Path
The Virtex-II Pro IOB input path routes input signals directly
to internal logic and / or through an optional input flip-flop or
latch, or through the DDR input registers. An optional delay
element at the D-input of the storage element eliminates
pad-to-pad hold time. The delay is matched to the internal
clock-distribution delay of the Virtex-II Pro device, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signaling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, V
PAD
constraints on which standards can be used in the same
bank. See I/O banking description.
Output Path
The output path includes a 3-state output buffer that drives
V CCAUX = 2.5V
the output signal onto the pad. The output and / or the
V CCINT = 1.5V
3-state signal can be routed to the buffer directly from the
internal logic or through an output / 3-state flip-flop or latch,
DS031_24_100900
or through the DDR output / 3-state registers.
Each output driver can be individually programmed for a
wide range of low-voltage signaling standards. In most sig-
naling standards, the output High voltage depends on an
transients.
externally supplied V
imposes constraints on which standards can be used in the
same bank. See I/O banking description.
I/O Banking
Some of the I/O standards described above require V
and V
voltages. These voltages are externally supplied
REF
and connected to device pins that serve groups of IOB
blocks, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Eight I/O banks result from dividing each edge of the FPGA
into two banks, as shown in
bank has multiple V
nected to the same voltage. This voltage is determined by
the output standards in use.
www.xilinx.com
12 mA
16 mA
24 mA
12 mA
16 mA
24 mA
12 mA
16 mA
24 mA
12 mA
16 mA
n/a
12 mA
16 mA
n/a
. The need to supply V
imposes
REF
REF
voltage. The need to supply V
CCO
Figure 24
and
Figure
25. Each
pins, all of which must be con-
CCO
Module 2 of 4
CCO
CCO
28