XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 38

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
DS083 (v4.7) November 5, 2007
Product Specification
Figure 22: LVTTL, LVCMOS, or PCI SelectIO-Ultra
Program
Delay
R
OBUF
registers
Shared
Program
Current
by all
(O/T) CLK1
(O/T) CLK2
V CCO
(O/T) CE
IBUF
(O/T) 1
(O/T) 2
V CCO
REV
SR
Standard
Clamp
Diode
Figure 21: Register / Latch Configuration in an IOB Block
V CCO
40KΩ –
40KΩ –
120KΩ
120KΩ
Keeper
Weak
V CCAUX = 2.5V
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
V CCINT = 1.5V
DS083-2_07_101801
D1
CE
CK1
D2
CE
CK2
SR REV
SR REV
www.xilinx.com
FF
LATCH
FF
LATCH
PAD
Q1
Q2
Attribute INIT1
Attribute INIT1
Input/Output Individual Options
Each device pad has optional pull-up/pull-down resistors
and weak-keeper circuit in the LVTTL, LVCMOS, and PCI
SelectIO-Ultra configurations, as illustrated in
Values of the optional pull-up and pull-down resistors fall
within a range of 40 KΩ to 120 KΩ when V
2.38V to 2.63V only). The clamp diodes are always present,
even when power is not.
The optional weak-keeper circuit is connected to each user
I/O pad. When selected, the circuit monitors the voltage on
the pad and weakly drives the pin High or Low. If the pin is
connected to a multiple-source signal, the weak-keeper
holds the signal in its last state if all drivers are disabled.
Maintaining a valid logic level in this way eliminates bus
chatter. An enabled pull-up or pull-down overrides the
weak-keeper circuit.
LVCMOS25 sinks and sources current up to 24 mA. The
current is programmable (see
slew rate controls for each output driver minimize bus tran-
sients. For LVDCI and LVDCI_DV2 standards, drive strength
and slew rate controls are not available.
DDR MUX
FF1
FF2
INIT0
SRHIGH
SRLOW
INIT0
SRHIGH
SRLOW
Reset Type
Table
SYNC
ASYNC
DS031_25_110300
11). Drive strength and
(OQ or TQ)
CCO
= 2.5V (from
Module 2 of 4
Figure
22.
27

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