XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
(O/T) 1
(O/T) CE
(O/T) CLK1
SR
Shared
by all
registers
REV
(O/T) CLK2
(O/T) 2
Figure 21: Register / Latch Configuration in an IOB Block
V CCO
Clamp
OBUF
Diode
V CCO
Program
Current
V CCO
Program
Delay
IBUF
Figure 22: LVTTL, LVCMOS, or PCI SelectIO-Ultra
Standard
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Attribute INIT1
INIT0
FF
SRHIGH
LATCH
SRLOW
Q1
D1
CE
CK1
SR REV
FF1
DDR MUX
FF2
FF
LATCH
D2
Q2
CE
Attribute INIT1
CK2
INIT0
SR REV
SRHIGH
SRLOW
Input/Output Individual Options
Each device pad has optional pull-up/pull-down resistors
and weak-keeper circuit in the LVTTL, LVCMOS, and PCI
SelectIO-Ultra configurations, as illustrated in
Values of the optional pull-up and pull-down resistors fall
within a range of 40 KΩ to 120 KΩ when V
Weak
Keeper
2.38V to 2.63V only). The clamp diodes are always present,
even when power is not.
40KΩ –
120KΩ
The optional weak-keeper circuit is connected to each user
I/O pad. When selected, the circuit monitors the voltage on
PAD
the pad and weakly drives the pin High or Low. If the pin is
connected to a multiple-source signal, the weak-keeper
40KΩ –
holds the signal in its last state if all drivers are disabled.
120KΩ
Maintaining a valid logic level in this way eliminates bus
V CCAUX = 2.5V
chatter. An enabled pull-up or pull-down overrides the
V CCINT = 1.5V
weak-keeper circuit.
LVCMOS25 sinks and sources current up to 24 mA. The
DS083-2_07_101801
current is programmable (see
slew rate controls for each output driver minimize bus tran-
sients. For LVDCI and LVDCI_DV2 standards, drive strength
and slew rate controls are not available.
www.xilinx.com
(OQ or TQ)
Reset Type
SYNC
ASYNC
DS031_25_110300
Figure
22.
= 2.5V (from
CCO
Table
11). Drive strength and
Module 2 of 4
27