XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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Functional Description: Processor Block
This section briefly describes the interfaces and compo-
nents of the Processor Block. The subsequent section,
Functional
Description:
Embedded PowerPC 405 Core
beginning on
page
20, offers a summary of major PPC405
core features. For an in-depth discussion on both the Pro-
cessor Block and PPC405, see tthe
and the
Reference Guide
PowerPC 405 Processor Block
Reference Guide
available on the Xilinx website at
.
http://www.xilinx.com
Processor Block Overview
Figure 14
shows the internal architecture of the Processor
Block.
CPU-FPGA Interfaces
BRAM
Control
PPC 405
Core
BRAM
Interface Logic
Processor Block = CPU Core + Interface Logic + CPU-FPGA Interface
Figure 14: Processor Block Architecture
Within the Virtex-II Pro Processor Block, there are four com-
ponents:
Embedded IBM PowerPC 405-D5 RISC CPU core
On-Chip Memory (OCM) controllers and interfaces
Clock/control interface logic
CPU-FPGA Interfaces
Embedded PowerPC 405 RISC Core
The PowerPC 405D5 core is a 0.13 µm implementation of
the IBM PowerPC 405D4 core. The advanced process tech-
nology enables the embedded PowerPC 405 (PPC405)
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
core to operate at 300+ MHz while maintaining low power
consumption. Specially designed interface logic integrates
the core with the surrounding CLBs, block RAMs, and gen-
eral routing resources. Up to four Processor Blocks can be
available in a single Virtex-II Pro device.
The embedded PPC405 core implements the PowerPC
User Instruction Set Architecture (UISA), user-level regis-
PowerPC Processor
ters, programming model, data types, and addressing
modes for 32-bit fixed-point operations. 64-bit operations,
auxiliary processor operations, and floating-point opera-
tions are trapped and can be emulated in software.
Most of the PPC405 core features are compatible with the
specifications for the PowerPC Virtual Environment
Architecture (VEA) and Operating Environment Architecture
(OEA). They also provide a number of optimizations and
extensions to the lower layers of the PowerPC Architecture.
The full architecture of the PPC405 is defined by the
PowerPC Embedded Environment and PowerPC UISA
documentation, available from IBM.
BRAM
On-Chip Memory (OCM) Controllers
Introduction
The OCM controllers serve as dedicated interfaces
between the block RAMs in the FPGA fabric (see
Block SelectRAM+ Resources, page
available on the embedded PPC405 core. The OCM signals
on the PPC405 core are designed to provide very quick
access to a fixed amount of instruction and data memory
space. The OCM controller provides an interface to both the
64-bit Instruction-Side Block RAM (ISBRAM) and the 32-bit
Data-Side Block RAM (DSBRAM). The designer can
choose to implement:
ISBRAM only
DSBRAM only
Both ISBRAM and DSBRAM
BRAM
No ISBRAM and no DSBRAM
One of OCM’s primary advantages is that it guarantees a
fixed latency of execution for a higher level of determinism.
Additionally, it reduces cache pollution and thrashing, since
DS083-2_03a_060701
the cache remains available for caching code from other
memory resources.
Typical applications for DSOCM include scratch-pad mem-
ory, as well as use of the dual-port feature of block RAM to
enable bidirectional data transfer between processor and
FPGA. Typical applications for ISOCM include storage of
interrupt service routines.
Functional Features
Common Features
Separate Instruction and Data memory interface
between processor core and BRAMs in FPGA
Dedicated interface to Device Control Register (DCR)
bus for ISOCM and DSOCM
www.xilinx.com
18 Kb
44) and OCM signals
Module 2 of 4
18