XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
1
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R
Virtex-II Pro / Virtex-II Pro X Device/Package Combinations and Maximum I/Os
Offerings include ball grid array (BGA) packages with
1.0 mm pitch. In addition to traditional wire-bond intercon-
nect (FG/FGG packages), flip-chip interconnect (FF pack-
ages) is used in some of the BGA offerings. Flip-chip
interconnect construction supports more I/Os than are pos-
sible in wire-bond versions of similar packages, providing a
high pin count and excellent power dissipation.
The device/package combination table
maximum number of user I/Os and RocketIO / RocketIO X
MGTs for each device and package using wire-bond or
flip-chip technology.
Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os
FG256/
FG456/
(1)
Package
FGG256
FGG456
Pitch (mm)
1.00
1.00
Size (mm)
17 x 17
23 x 23
XC2VP2
140 / 4
156 / 4
XC2VP4
140 / 4
248 / 4
XC2VP7
248 / 8
XC2VP20
XC2VPX20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
Notes:
1.
Wirebond packages FG256, FG456, and FG676 are also available in Pb-free versions FGG256, FGG456, and FGG676. See
Examples
for details on how to order.
2.
Virtex-II Pro X device is equipped with RocketIO X transceiver cores.
3.
The RocketIO transceivers in devices in the FF1148 and FF1696 packages are not bonded out to the package pins.
Maximum Performance
Maximum performance of the RocketIO / RocketIO X transceiver and the PowerPC processor block varies, depending on
package style and speed grade. See
Characteristics
contains the rest of the FPGA fabric performance parameters.
Table 4: Maximum RocketIO / RocketIO X Transceiver and Processor Block Performance
Device
RocketIO X Transceiver FlipChip (FF)
RocketIO Transceiver FlipChip (FF)
RocketIO Transceiver Wirebond (FG)
PowerPC Processor Block
Notes:
1.
-7 speed grade devices are not available in Industrial grade.
2.
IMPORTANT! When CPMC405CLOCK runs at speeds greater than 350 MHz in -7 Commercial grade dual-processor devices, or greater than
300 MHz in -6 Industrial grade dual-processor devices, users must implement the technology presented in XAPP755, “PowerPC 405 Clock Macro for
-7(C) and -6(I) Speed Grade Dual-Processor Devices.” Refer to
3.
XC2VPX70 is only available at fixed 4.25 Gb/s baud rate.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Introduction and Overview
The FF1148 and FF1696 packages have no RocketIO
transceivers bonded out. Extra SelectIO-Ultra resources
occupy available pins in these packages, resulting in a
higher user I/O count. These packages are available for the
XC2VP40, XC2VP50, and XC2VP100 devices only.
The I/Os per package count includes all user I/Os except
the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
(Table
3) details the
PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
DXP, and RSVD), VBATT, and the RocketIO / RocketIO X
transceiver pins.
FG676
FF672
FF896
FF1152
1.00
1.00
1.00
1.00
26 x 26
27 x 27
31 x 31
35 x 35
204 / 4
348 / 4
396 / 8
396 / 8
404 / 8
556 / 8
564 / 8
(2)
552 / 8
416 / 8
556 / 8
644 / 8
416 / 8
692 / 12
692 / 16
Table 4
for details.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching
Speed Grade
(1)
-7
N/A
6.25
3.125
3.125
2.5
(2)
400
350
Table 1
to identify dual-processor devices.
www.xilinx.com
FF1148
FF1517
FF1704
1.00
1.00
1.00
35 x 35
40 x 40
42.5 x 42.5
(3)
804 / 0
(3)
812 / 0
852 / 16
964 / 16
996 / 20
992 / 20
1,040 / 20
Virtex-II Pro Ordering
-6
-5
(3)
(3)
4.25
2.0
2.5
2.0
(2)
300
FF1696
1.00
42.5 x 42.5
(2)
(3)
1,164 / 0
Units
Gb/s
Gb/s
Gb/s
MHz
Module 1 of 4
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