XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
18-Bit x 18-Bit Multipliers
Introduction
A Virtex-II Pro multiplier block is an 18-bit by 18-bit 2’s com-
plement signed multiplier. Virtex-II Pro devices incorporate
many embedded multiplier blocks. These multipliers can be
associated with an 18 Kb block SelectRAM+ resource or
can be used independently. They are optimized for
high-speed operations and have a lower power consump-
tion compared to an 18-bit x 18-bit multiplier in slices.
Each SelectRAM+ memory and multiplier block is tied to
four switch matrices, as shown in
Figure
Switch
Matrix
Switch
Matrix
18-Kbit block
SelectRAM
Switch
Matrix
Switch
Matrix
Figure 53: SelectRAM+ and Multiplier Blocks
Association With Block SelectRAM+ Memory
The interconnect is designed to allow SelectRAM+ memory
and multiplier blocks to be used at the same time, but some
interconnect is shared between the SelectRAM+ and the
multiplier. Thus, SelectRAM+ memory can be used only up
to 18 bits wide when the multiplier is used, because the mul-
tiplier shares inputs with the upper data bits of the
SelectRAM+ memory.
This sharing of the interconnect is optimized for an
18-bit-wide block SelectRAM+ resource feeding the multi-
plier. The use of SelectRAM+ memory and the multiplier
with an accumulator in LUTs allows for implementation of a
digital signal processor (DSP) multiplier-accumulator (MAC)
function, which is commonly used in finite and infinite
impulse response (FIR and IIR) digital filters.
Configuration
The multiplier block is an 18-bit by 18-bit signed multiplier
(2's complement). Both A and B are 18-bit-wide inputs, and
the output is 36 bits.
Figure 54
shows a multiplier block.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
A[17:0]
B[17:0]
53.
Locations / Organization
Multiplier organization is identical to the 18 Kb SelectRAM+
organization, because each multiplier is associated with an
18 Kb block SelectRAM+ resource.
Table 26: Multiplier Resources
Device
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP30
XC2VPX20
XC2VP40
DS031_33_101000
XC2VP50
XC2VP70
XC2VPX70
XC2VP100
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to
Global Clock Multiplexer Buffers
Virtex-II Pro devices have 16 clock input pins that can also
be used as regular user I/Os. Eight clock pads center on
both the top edge and the bottom edge of the device, as
illustrated in
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II Pro
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
www.xilinx.com
Multiplier Block
MULT 18 x 18
DS031_40_100400
Figure 54: Multiplier Block
Columns
Total Multipliers
4
4
6
8
8
136
8
10
192
12
232
14
328
14
308
16
444
Configurable Logic Blocks (CLBs), page
Figure
55.
Module 2 of 4
P[35:0]
12
28
44
88
88
35).
48