XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Table 4: Virtex-II Pro Pin Definitions (Continued)
Pin Name
Direction
BREFCLKN,
Input
(2)
BREFCLKP
VTRXPAD#
Input
VTTXPAD#
Input
GNDA#
Input
RXPPAD#
Input
RXNPAD#
Input
TXPPAD#
Output
TXNPAD#
Output
Notes:
1. All dedicated pins (JTAG and configuration) are powered by V
2. Virtex-II Pro X devices XC2VPX20 and XC2VPX70 only. Each BREFCLK(N/P) differential clock input pair takes the place of one
regular Virtex-II Pro dual-function IO/GCLKx(S/P) pair on each side of the chip (top or bottom). For RocketIO BREFCLK, see section
BREFCLK Pin Definitions (RocketIO Only)
BREFCLK Pin Definitions (RocketIO Only)
These dedicated clocks use the same clock inputs for all packages:
P
GCLK4S
BREFCLK
N
GCLK5P
Top
P
GCLK2S
BREFCLK2
N
GCLK3P
For detailed information about using BREFCLK/BREFCLK2, including routing considerations and pin numbers for all
package types, refer to Chapter 2, "Digital Design Considerations," in the
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Description
Differential clock input that clocks the RocketIO X MGTs populating the same side of
the chip (top or bottom). Can also drive DCMs for RocketIO X MGT use.
Receive termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
Transmit termination supply for the RocketIO multi-gigabit transceiver (1.8V - 2.8V).
Ground for the analog circuitry of the RocketIO multi-gigabit transceiver.
Positive differential receive port of the RocketIO multi-gigabit transceiver.
Negative differential receive port of the RocketIO multi-gigabit transceiver.
Positive differential transmit port of the RocketIO multi-gigabit transceiver.
Negative differential transmit port of the RocketIO multi-gigabit transceiver.
(independent of the bank V
CCAUX
immediately following.
P
BREFCLK
N
Bottom
P
BREFCLK2
N
RocketIO Transceiver User Guide
www.xilinx.com
voltage).
CCO
GCLK6P
GCLK7S
GCLK0P
GCLK1S
.
Module 4 of 4
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