XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Configurable Logic Blocks (CLBs)
The Virtex-II Pro configurable logic blocks (CLB) are orga-
nized in an array and are used to build combinatorial and
synchronous logic designs. Each CLB element is tied to a
switch matrix to access the general routing matrix, as
shown in
Figure
32. A CLB element comprises 4 similar
slices, with fast local feedback within the CLB. The four
slices are split in two columns of two slices with two inde-
pendent carry logic chains and one common shift chain.
COUT
TBUF
TBUF
Slice
X1Y1
Slice
X1Y0
COUT
Switch
Matrix
SHIFT
CIN
Slice
X0Y1
Slice
X0Y0
CIN
Figure 32: Virtex-II Pro CLB Element
Slice Description
Each slice includes two 4-input function generators, carry
logic, arithmetic logic gates, wide function multiplexers and
two storage elements. As shown in
function generator is programmable as a 4-input LUT, 16
bits of distributed SelectRAM+ memory, or a 16-bit vari-
able-tap shift register element.
The output from the function generator in each slice drives
both the slice output and the D input of the storage element.
Figure 34
shows a more detailed view of a single slice.
ORCY
RAM16
MUXFx
SRL16
CY
LUT
G
RAM16
MUXF5
SRL16
CY
LUT
F
Arithmetic Logic
Figure 33: Virtex-II Pro Slice Configuration
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Configurations
Look-Up Table
Virtex-II Pro function generators are implemented as
4-input look-up tables (LUTs). Four independent inputs are
provided to each of the two function generators in a slice (F
and G). These function generators are each capable of
implementing any arbitrarily defined boolean function of four
inputs. The propagation delay is therefore independent of
the function implemented. Signals from the function gener-
ators can exit the slice (X or Y output), can input the XOR
dedicated gate (see arithmetic logic), or input the carry-logic
multiplexer (see fast look-ahead carry logic), or feed the D
input of the storage element, or go to the MUXF5 (not
shown in
In addition to the basic LUTs, the Virtex-II Pro slice contains
logic (MUXF5 and MUXFX multiplexers) that combines
function generators to provide any function of five, six,
seven, or eight inputs. The MUXFX is either MUXF6,
MUXF7, or MUXF8 according to the slice considered in the
CLB. Selected functions up to nine inputs (MUXF5 multi-
Fast
plexer) can be implemented in one slice. The MUXFX can
Connects
also be a MUXF6, MUXF7, or MUXF8 multiplexer to map
to neighbors
any function of six, seven, or eight inputs and selected wide
DS083-2_32_122001
logic functions.
Register/Latch
The storage elements in a Virtex-II Pro slice can be config-
ured either as edge-triggered D-type flip-flops or as
level-sensitive latches. The D input can be directly driven by
the X or Y output via the DX or DY input, or by the slice
Figure
33, each 4-input
inputs bypassing the function generators via the BX or BY
input. The clock enable signal (CE) is active High by default.
If left unconnected, the clock enable for that storage ele-
ment defaults to the active state.
In addition to clock (CK) and clock enable (CE) signals,
each slice has set and reset signals (SR and BY slice
inputs). SR forces the storage element into the state speci-
fied by the attribute SRHIGH or SRLOW. SRHIGH forces a
logic 1 when SR is asserted. SRLOW forces a logic 0. When
SR is used, an optional second input (BY) forces the stor-
age element into the opposite state via the REV pin. The
reset condition is predominant over the set condition. (See
Figure
35.)
Register/
Latch
The initial state after configuration or global initial state is
defined by a separate INIT0 and INIT1 attribute. By default,
setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1. For each slice, set and reset
can be set to be synchronous or asynchronous.
Virtex-II Pro devices also have the ability to set INIT0 and
Register/
INIT1 independent of SRHIGH and SRLOW.
Latch
The control signals clock (CLK), clock enable (CE) and
set/reset (SR) are common to both storage elements in one
slice. All of the control signals have independent polarity. Any
DS083-2_31_122001
inverter placed on a control input is automatically absorbed.
www.xilinx.com
Figure
34).
Module 2 of 4
35