XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 


Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Routing
DCM and MGT Locations/Organization
Virtex-II Pro DCMs and serial transceivers (MGTs) are
placed on the top and bottom of each block RAM and multi-
plier column in some combination, as shown in
The number of DCMs and RocketIO transceivers total twice
the number of block RAM columns in the device. Refer to
Figure 52, page 47
for an illustration of this in the XC2VP4
device.
Table 31: DCM and MGT Organization
Block RAM
Device
Columns
DCMs
XC2VP2
4
XC2VP4
4
XC2VP7
6
XC2VP20
8
XC2VPX20
8
XC2VP30
8
XC2VP40
10
XC2VP50
12
XC2VP70
14
XC2VPX70
14
XC2VP100
16
24 Horizontal Long Lines
24 Vertical Long Lines
120 Horizontal Hex Lines
120 Vertical Hex Lines
40 Horizontal Double Lines
40 Vertical Double Lines
16 Direct Connections
(total in all four directions)
8 Fast Connects
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
Place-and-route software takes advantage of this regular
array to deliver optimum system performance and fast com-
pile times. The segmented routing resources are essential
to guarantee IP cores portability and to efficiently handle an
Table
31.
incremental design flow that is based on modular imple-
mentations. Total design time is reduced due to fewer and
shorter design iterations.
Hierarchical Routing Resources
Most Virtex-II Pro signals are routed using the global rout-
ing resources, which are located in horizontal and vertical
MGTs
routing channels between each switch matrix.
4
4
As shown in
4
4
ered programmable interconnections, with a number of
resources counted between any two adjacent switch matrix
4
8
rows or columns. Fanout has minimal impact on the perfor-
8
8
mance of each net.
8
8
•
The long lines are bidirectional wires that distribute
8
8
signals across the device. Vertical and horizontal long
lines span the full height and width of the device.
8
12
•
The hex lines route signals to every third or sixth block
8
16
away in all four directions. Organized in a staggered
8
20
pattern, hex lines can only be driven from one end.
Hex-line signals can be accessed either at the
8
20
endpoints or at the midpoint (three blocks from the
12
20
source).
Figure 64: Hierarchical Routing Resources
www.xilinx.com
Figure 64, page
54, Virtex-II Pro has fully buff-
DS031_60_110200
Module 2 of 4
54

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