XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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R
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current
during power-on to insure proper device initialization. The
actual current consumed depends on the power-on ramp
rate of the power supply.
The V
power supply must ramp on, monotonically, no
CCINT
faster than 200 μs and no slower than 50 ms. Ramp-on is
defined as: 0 V
to minimum supply voltages (see
DC
Table
2).
V
and V
can power on at any ramp rate. Power
CCAUX
CCO
supplies can be turned on in any sequence.
Table 5: Power-On Current for Virtex-II Pro Devices
Symbol
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
I
500
500
500
CCINTMIN
I
250
250
250
CCAUXMIN
I
100
100
100
CCOMIN
Notes:
1. Power-on current parameter values are specified for Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.5.
2. I
values listed here apply to the entire device (all banks).
CCOMIN
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential.
Consult Xilinx Application Note
XAPP623
mation on power distribution system design.
V
powers critical resources in the FPGA. Therefore,
CCAUX
this supply voltage is especially susceptible to power supply
noise. V
can share a power plane with V
CCAUX
if V
does not have excessive noise. Staying within
CCO
simultaneously switching output (SSO) limits is essential for
keeping power supply noise to a minimum. Refer to
DS083 (v4.7) November 5, 2007
Product Specification
Table 5
shows the minimum current required by Virtex-II Pro
devices for proper power-on and configuration.
If the current minimums shown in
device powers on properly after all three supplies have
passed through their power-on reset threshold voltages.
Once initialized and configured, use the power calculator to
estimate current drain on these supplies.
For more information on V
mode, refer to Chapter 3 in the Virtex-II Pro Platform FPGA
User Guide.
Device
600
600
800
1050
250
250
250
250
100
100
100
100
, “Managing Ground Bounce in Large FPGAs,” to
XAPP689
for detailed infor-
determine the number of simultaneously switching outputs
allowed per bank at the package level.
Changes in V
should take place at a rate no faster than 10 mV per milli-
, but only
second.
CCO
Recommended practices that can help reduce jitter and
period distortion are described in Xilinx Answer Record
13756.
www.xilinx.com
Table 5
are met, the
, V
, and configuration
CCAUX
CCO
1250
1700
1700
2200
250
250
250
250
100
100
100
100
voltage beyond 200 mV peak-to-peak
CCAUX
Module 3 of 4
Units
mA
mA
mA
5