XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 76
Manufacturer Part Number
IC FPGA VIRTEX-II PRO 896-FBGA
Specifications of XC2VP7-5FFG896I
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current
during power-on to insure proper device initialization. The
actual current consumed depends on the power-on ramp
rate of the power supply.
faster than 200 μs and no slower than 50 ms. Ramp-on is
defined as: 0 V
supplies can be turned on in any sequence.
Table 5: Power-On Current for Virtex-II Pro Devices
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is essential.
Consult Xilinx Application Note
mation on power distribution system design.
this supply voltage is especially susceptible to power supply
simultaneously switching output (SSO) limits is essential for
keeping power supply noise to a minimum. Refer to
DS083 (v4.7) November 5, 2007
1. Power-on current parameter values are specified for Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.5.
powers critical resources in the FPGA. Therefore,
does not have excessive noise. Staying within
values listed here apply to the entire device (all banks).
XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VPX20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VPX70 XC2VP100
power supply must ramp on, monotonically, no
can share a power plane with V
can power on at any ramp rate. Power
to minimum supply voltages (see
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: DC and Switching Characteristics
for detailed infor-
, but only
devices for proper power-on and configuration.
If the current minimums shown in
device powers on properly after all three supplies have
passed through their power-on reset threshold voltages.
Once initialized and configured, use the power calculator to
estimate current drain on these supplies.
For more information on V
mode, refer to Chapter 3 in the Virtex-II Pro Platform FPGA
determine the number of simultaneously switching outputs
allowed per bank at the package level.
Changes in V
should take place at a rate no faster than 10 mV per milli-
Recommended practices that can help reduce jitter and
period distortion are described in Xilinx Answer Record
shows the minimum current required by Virtex-II Pro
, “Managing Ground Bounce in Large FPGAs,” to
voltage beyond 200 mV peak-to-peak
, and configuration
are met, the
Module 3 of 4