XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
Page 421
422
Page 422
423
Page 423
424
Page 424
425
Page 425
426
Page 426
427
Page 427
428
Page 428
429
Page 429
430
Page 430
Page 429/430

Download datasheet (4Mb)Embed
PrevNext
R
Revision History
This section records the change history for this module of the data sheet.
Date
Version
01/31/02
1.0
Initial Xilinx release.
08/14/02
2.0
Added package and pinout information for new devices.
08/27/02
2.1
09/27/02
2.2
Corrected
692 to 644.
11/20/02
2.3
Added Number of Differential Pairs data to
12/03/02
2.4
Corrections in
01/20/03
2.5
Added and removed package/pinout information for existing devices:
05/19/03
2.5.1
06/19/03
2.5.3
08/25/03
2.5.5
12/10/03
3.0
02/19/04
3.1
03/09/04
3.1.1
06/30/04
4.0
Merged in DS110-4 (Module 4 of Virtex-II Pro X data sheet). Added data on available
Pb-free packages and updated package diagrams for affected devices.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Pinout Information
Updated SelectIO-Ultra information in
Corrected direction for RXNPAD and TXPPAD in
Table 2
and
Table 3
entries for XC2VP30, FF1152 package, maximum I/Os from
Table
4:
Reclassified GCLKx (S/P) pins as Input/Output, since these pins can be used as
normal I/Os if not used as clocks.
Added cautionary note to PWRDWN_B pin, indicating that this function is not
supported.
In
Table
1, added FG676 package information.
In
Table
3, added FG676 package option for XC2VP20, XC2VP30, and XC2VP40.
In
Table
12, removed FF1517 package option for XC2VP40.
Added FG676 package pinouts
(Table
Added package diagram
(Figure
3) for FG676 package.
Added section
BREFCLK Pin Definitions, page
Added clarification to
Table 4
and all device pinout tables regarding the dual-use
nature of pins D0/DIN and BUSY/DOUT during configuration.
Added notation of "open-drain" to TDO pin in
The final GND pin in each of six pinout tables was inadvertently deleted in v2.5.1. This
revision restores the deleted GND pins as follows:
-
Pin A1,
Table 6, page 16
(FG456)
-
Pin AF26,
Table 7, page 30
(FG676)
-
Pin AN34,
Table 10, page 98
(FF1152)
-
Pin E1,
Table 11, page 130
(FF1148)
-
Pin C38,
Table 12, page 162
(FF1517)
-
Pin E1,
Table 14, page 253
(FF1696)
Table
4: Deleted Note 2, obsolete. There is only one GNDA pin per MGT.
Table
4: Deleted pins ALT_VRP and ALT_VRN. Not used in Virtex-II Pro FPGAs.
XC2VP2 through XC2VP70 speed grades -5, -6, and -7, and XC2VP100 speed grades
-5 and -6, are released to Production status.
Table
4, signal descriptions column:
-
For signals TDI, TMS, and TCK, added: Pins are 3.3V-compatible.
-
For signals M2, M1, M0, added: Tie to 3.3V only with 100Ω series resistor.
No toggling during or after configuration.
-
For signal TDO, added: No internal pull-up. External pull-up to 3.3V OK with
resistor greater than 200Ω.
Recompiled for backward compatibility with Acrobat 4 and above. No content
changes.
www.xilinx.com
Revision
Table
4. (Table deleted in v2.3.)
Table 4
(formerly Table 5).
Table
3. Removed former Table 4.
7) for XC2VP20, XC2VP30, and XC2VP40.
5.
Table
4.
Module 4 of 4
301