XC2VP7-5FFG896I Xilinx Inc, XC2VP7-5FFG896I Datasheet - Page 50

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XC2VP7-5FFG896I

Manufacturer Part Number
XC2VP7-5FFG896I
Description
IC FPGA VIRTEX-II PRO 896-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-II Pror
Datasheet

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells
11088
Number Of Labs/clbs
1232
Total Ram Bits
811008
Number Of I /o
396
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
896-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
R
Shift Registers
Each function generator can also be configured as a 16-bit
shift register. The write operation is synchronous with a
clock input (CLK) and an optional clock enable, as shown in
Figure
39. A dynamic read access is performed through the
4-bit address bus, A[3:0]. The configurable 16-bit shift regis-
ter cannot be set or reset. The read is asynchronous; how-
ever, the storage element or flip-flop is available to
implement a synchronous read. Any of the 16 bits can be
read out asynchronously by varying the address. The stor-
age element should always be used with a constant
address. For example, when building an 8-bit shift register
and configuring the addresses to point to the 7th bit, the 8th
bit can be the flip-flop. The overall system performance is
improved by using the superior clock-to-out of the flip-flops.
SRLC16
SHIFTIN
SHIFT-REG
4
D
A[3:0]
A[4:1]
MC15
DI
WS
D(BY)
WSG
CE (SR)
WE
CLK
CK
SHIFTOUT
Figure 39: Shift Register Configurations
An additional dedicated connection between shift registers
allows connecting the last bit of one shift register to the first
bit of the next, without using the ordinary LUT output. (See
Figure
40.) Longer shift registers can be built with dynamic
access to any bit in the chain. The shift register chaining
and the MUXF5, MUXF6, and MUXF7 multiplexers allow up
to a 128-bit shift register with addressable access to be
implemented in one CLB.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
1 Shift Chain
in CLB
Output
Registered
D
Q
Output
(optional)
SRLC16
DS031_05_110600
SRLC16
SRLC16
SRLC16
www.xilinx.com
DI
D
IN
SRLC16
MC15
DI
D
SRLC16
MC15
SLICE S3
SHIFTOUT
SHIFTIN
DI
D
SRLC16
MC15
DI
D
SRLC16
MC15
SLICE S2
SHIFTOUT
SHIFTIN
DI
D
FF
MC15
DI
D
FF
MC15
SLICE S1
SHIFTOUT
SHIFTIN
DI
D
FF
MC15
DI
D
FF
MC15
SLICE S0
OUT
CASCADABLE OUT
Figure 40: Cascadable Shift Register
FF
FF
FF
FF
CLB
DS031_06_110200
Module 2 of 4
39

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