XC2VP7-5FFG896I

Manufacturer Part NumberXC2VP7-5FFG896I
DescriptionIC FPGA VIRTEX-II PRO 896-FBGA
ManufacturerXilinx Inc
SeriesVirtex™-II Pro
XC2VP7-5FFG896I datasheet
 

Specifications of XC2VP7-5FFG896I

Number Of Logic Elements/cells11088Number Of Labs/clbs1232
Total Ram Bits811008Number Of I /o396
Voltage - Supply1.425 V ~ 1.575 VMounting TypeSurface Mount
Operating Temperature-40°C ~ 100°CPackage / Case896-BBGA, FCBGA
Lead Free Status / RoHS StatusLead free / RoHS CompliantNumber Of Gates-
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Table 5: Clock Ratios for Various Data Widths
Frequency Ratio of
Fabric Data Width
USRCLK:USRCLK2
1-byte
1:2
2-byte
1:1
4-byte
2:1
Notes:
1.
Each edge of slower clock must align with falling edge of
faster clock.
FPGA Transmit Interface
The FPGA can send either one, two, or four characters of
data to the transmitter. Each character can be either 8 bits
or 10 bits wide. If 8-bit data is applied, the additional inputs
become control signals for the 8B/10B encoder. When the
8B/10B encoder is bypassed, the 10-bit character order is
generated as follows:
TXCHARDISPMODE[0]
(first bit transmitted)
TXCHARDISPVAL[0]
TXDATA[7:0]
(last bit transmitted is TXDATA[0])
Disparity Control
The 8B/10B encoder is initialized with a negative running
disparity. Unique control allows forcing the current running
disparity state.
TXRUNDISP signals its current running disparity. This may
be useful in those cases where there is a need to manipu-
late the initial running disparity value.
Bits TXCHARDISPMODE and TXCHARDISPVAL control
the generation of running disparity before each byte.
For example, the transceiver can generate the sequence
K28.5+ K28.5+ K28.5– K28.5–
or
K28.5– K28.5– K28.5+ K28.5+
by specifying inverted running disparity for the second and
fourth bytes.
Transmit FIFO
Proper operation of the circuit is only possible if the FPGA
clock (TXUSRCLK) is frequency-locked to the reference
clock (REFCLK). Phase variations up to one clock cycle are
allowable. The FIFO has a depth of four. Overflow or under-
flow conditions are detected and signaled at the interface.
Bypassing of this FIFO is programmable.
8B/10B Encoder
Note: In the RocketIO transceiver, the most-significant byte is
sent first; in the RocketIO X transceiver, the least-signifi-
cant byte is sent first.
A bypassable 8B/10B encoder is included. The encoder uses
the same 256 data characters and 12 control characters
used by Gigabit Ethernet, Fibre Channel, and InfiniBand.
DS083 (v4.7) November 5, 2007
Product Specification
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
The encoder accepts 8 bits of data along with a K-character
signal for a total of 9 bits per character applied, and
generates a 10 bit character for transmission. If the
K-character signal is High, the data is encoded into one of
(1)
the twelve possible K-characters available in the 8B/10B
code. If the K-character input is Low, the 8 bits are encoded
as standard data. If the K-character input is High, and a
(1)
user applies other than one of the twelve possible
combinations, TXKERR indicates the error.
8B/10B Decoder
Note: In the RocketIO transceiver, the most-significant byte is
sent first; in the RocketIO X transceiver, the
least-significant byte is sent first.
An optional 8B/10B decoder is included. A programmable
option allows the decoder to be bypassed. When the
8B/10B decoder is bypassed, the 10-bit character order is,
for example,
RXCHARISK[0]
RXRUNDISP[0]
RXDATA[7:0]
The decoder uses the same table that is used for Gigabit
Ethernet, Fibre Channel, and InfiniBand. In addition to
decoding all data and K-characters, the decoder has sev-
eral extra features. The decoder separately detects both
“disparity errors” and “out-of-band” errors. A disparity error
is the reception of 10-bit character that exists within the
8B/10B table but has an incorrect disparity. An out-of-band
error is the reception of a 10-bit character that does not exist
within the 8B/10B table. It is possible to obtain an
out-of-band error without having a disparity error. The
proper disparity is always computed for both legal and ille-
gal characters. The current running disparity is available at
the RXRUNDISP signal.
The 8B/10B decoder performs a unique operation if
out-of-band data is detected. If out-of-band data is
detected, the decoder signals the error and passes the ille-
gal 10-bits through and places them on the outputs. This
can be used for debugging purposes if desired.
The decoder also signals the reception of one of the 12 valid
K-characters. In addition, a programmable comma detect is
included. The comma detect signal registers a comma on
the receipt of any comma+, comma–, or both. Since the
comma is defined as a 7-bit character, this includes several
out-of-band characters. Another option allows the decoder
to detect only the three defined commas (K28.1, K28.5, and
K28.7) as comma+, comma–, or both. In total, there are six
possible options, three for valid commas and three for "any
comma."
Note that all bytes (1, 2, or 4) at the RX FPGA interface
each have their own individual 8B/10B indicators (K-charac-
ter, disparity error, out-of-band error, current running dispar-
ity, and comma detect).
Power Sequencing
www.xilinx.com
(first bit received)
(last bit received is RXDATA[0])
Module 2 of 4
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