pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 101

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

3.8.2
The following automatic modes are performed by the QuadLIU
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•
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3.8.3
The QuadLIU
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The error counters are buffered. Buffer updating is done in two modes:
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In the one-second mode an internal/external one-second timer updates these buffers and resets the counter to
accumulate the error events in the next one-second period. The error counter cannot overflow. Error events
occurring during an error counter reset are not lost.
3.8.4
A one-second timer interrupt can be generated internally to indicate that the enabled alarm status bits or the error
counters have to be checked. The one-second timer signal is output on port SEC/FSC if configured by
GPC1.CSFP(1:0) (GPC1). Optionally synchronization to an external second timer is possible which has to be
provided on pin SEC/FSC. Selecting the external second timer is done with GCR.SES.
Data Sheet
Automatic clock source switching (see also: In slave mode (LIM0.MAS = ´0´) the DCO-R synchronizes to the
recovered route clock. In case of loss-of-signal (LOS) the DCO-R switches to Master mode automatically. If bit
CMR1.DCS is set, automatic switching from the recovered route clock to SYNC is disabled. See also
Automatic transmit clock switching, see
Automatic local and remote loop switching based on In-Band loop codes, see
Code Violation Counter, status registers CVCL and CVCH
PRBS error counter, status registers BECL and BECH
One-second accumulation
On demand by handshake with writing to the DEC register
Automatic Modes
Error Counter
One-Second Timer
TM
offers two error counters where each of them has a length of 16 bit:
Chapter
3.9.3.
101
TM
:
Chapter
Functional Description
3.11.2.
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Table
24.
TM