pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 116

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

4
To maintain easy readability this chapter is divided into separate control register and status register sections.
The higher address part of all global registers is ´00
number 0 to 3 and is marked in the following tables with ´xx
Note: “RES” in the register schematics means reserved, not reset. If these bits are written then the value must be
Note: In all bit fields used in the register schematics and also in the table descriptions the most significant bit is the
4.1
Table 35
Register Short Name
IPC
GCR
GPC1
GPC2
GCM1
GCM2
GCM3
GCM4
GCM5
GCM6
GCM7
GCM8
GIMR
REGFP
REGFD
GPC3
GPC4
GPC5
GPC6
INBLDTR
CMDR
IMR1
IMR2
IMR3
IMR4
IMR6
Data Sheet
´0´.
left one and the least significant bit is the right one. Sometimes in the text a bit field with the name
“bitfieldname” is denoted as <bitfieldname>(MSB:LSB). For example: In register GPC2 the bit field FSS
consists on MDS(2:0).
Register Description
Detailed Control Register Description
Registers Overview
Register Long Name
Interrupt Port Configuration
Global Configuration Register
Global Port Configuration 1
Global Port Configuration Register 2
Global Clock Mode Register 1
Global Clock Mode Register 2
Global Clock Mode Register 3
Global Clock Mode Register 4
Global Clock Mode Register 5
Global Clock Mode Register 6
Global Clock Mode Register 7
Global Clock Mode Register 7
Global Interrupt Mask Register
Register Field Pointer
Register Field Data
Global Port Configuration Register 3
Global Port Configuration Register 4
Global Port Configuration Register 5
Global Port Configuration Register 6
In-Band Loop Detection Time Register
Command Register
Interrupt Mask Register 1
Interrupt Mask Register 2
Interrupt Mask Register 3
Interrupt Mask Register 4
Interrupt Mask Register 6
H
´, that of the port (channel) specific ones include the channel
116
H
´. So ´xx
H
´ has the values ´00
Offset Address
0008
0046
0085
008A
0092
0093
0094
0095
0096
0097
0098
0099
00A7
00BB
00BC
00D3
00D4
00D5
00D6
00D7
xx02
xx15
xx16
xx17
xx18
xx1A
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Description
´ up to ´03
Rev. 1.3, 2006-01-25
Page Number
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QuadLIU
PEF 22504
H
´.
TM