pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 114

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Figure 45
3.11.6
Alarm simulation does not affect the normal operation of the device. However, possible
not reported to the micro controller or to the remote end when the device is in the alarm simulation mode.
The alarm simulation and setting of the appropriate status bists is initiated by setting the bit MR0.SIM. For details
(differences between E1 and T1/J1 mode) see description in MR0. The following alarms are simulated:
•
•
•
Error counting and indication occurs while this bit is set. After it is reset all simulated error conditions disappear,
but the generated interrupt statuses are still pending until the corresponding interrupt status register is read.
Alarms like AIS and LOS are cleared automatically. Interrupt status registers and error counters are automatically
cleared on read.
3.12
Several signals are available on the multi function ports, see
(´0000
Four multi function ports (MFP) for RX - so called as RPA, RPB, RPC, RPC - and four MFPs for TX - XPA to XPD
- are implemented for every channel. The port levels are reflected in the appropriate bits of the register MFPI, see
MFPID
The functions of RPA, RPB, RPC and RPC are configured by PC1.RPC1(3:0) , PC2.RPC2(3:0), PC3.RPC2(3:0)
and PC4.RPC3(3:0) respectively. The functions of XPA to XPD are configured by PC1.XPC1(3:0) to
PC4.XPC2(3:0) respectively.
The actual logical state of the 8 multifunction ports can be read out using the register MFPI. This function together
with static output signal options in
pins.
If a port is configured as GPOH or GPOL the port level is set fix to high or low-level respectively.
Data Sheet
Loss-Of-Signal (LOS)
Alarm Indication Signal (AIS)
Code violation counter (HDB3 Code)
RL1/ROID
Receive Line
Interface
Transmit Line
Interface
b
´).
RL2
XL3
XL1
XL2
XL4
Payload Loop
Alarm Simulation
Multi Function Ports
Equalizer
Payload Loop
Table 34
DAC
Shaper,
Pulse
LBO
Recovery
Clock &
Data
DPLL
offers general purpose I/O functionality on unused multi function port
114
Decoder
Encoder
Table 34
A
H
and PC1. After reset, no function is selected
Dual Transmit Elastic Buffer
Dual Receive Elastic Buffer
DCO-X
C
internal
receive
clock
recovered
receive clock
DCO-R
G
J
real
Functional Description
F
internal
transmit
clock
Rev. 1.3, 2006-01-25
alarm conditions are
D
RCLK
%
E
Q LIU _pay load_loop
QuadLIU
PEF 22504
FCLKR
RDOP
RDON
XDIP
XDIN
FCLKX
TCLK
TM