pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 245

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 75
Basic Set Up
Master clocking mode
E1 mode select
Clock system configuration
Specification of line interface
Specification of transmit pulse mask
Line interface coding
Loss-of-signal detection/recovery conditions
Multi Function Port selection
Features like alarm simulation etc. are activated later. Transmission of alarms (e.g. AIS, remote alarm) and control
of synchronization in connection with consequent actions to remote end and internal system depend on the
activation procedure selected.
Note: Read access to unused register addresses: value should be ignored. Write access to unused register
Specific E1 Register Settings
The following is a suggestion for a basic configuration to meet most of the E1 requirements. Depending on different
applications and requirement any other configuration can be used.
Table 76
GPC6.COMP_DIS = ´1´
MR2.DAIS = ´1´
MR2.RTM = ´1´
MR5.TT0 = ´1´
MR5.XTM = ´1´
MR0.XC0/
MR0.RC0/
LIM1.DRS
MR3.CMI
PCD = ´0A
PCR = ´15
LIM1.RIL(2:0) = ´02
Attention: After the device configuration a software reset should be executed by setting of bits
7.5
After reset, the QuadLIU
to be set high. After the internal clocking is settled to T1/J1mode (takes up to 20 s), the following register values
are initialized:
T1/J1 Initialization
For a correct start up of the primary access interface a set of parameters specific to the system and hardware
environment must be programmed after RES goes inactive (high). Both the basic and the operational parameters
Data Sheet
addresses: should be avoided, or set to “00” hex. All control registers (except XS(16:1), CMDR, DEC) are of
type Read/Write.
H
H
CMDR.XRES/RRES.
´
´
Configuration Parameters (E1)
Line Interface Configuration (E1)
Device Configuration in T1/J1 Mode
H
´
TM
is initialized for E1 doubleframe format. To configure T1/J1 mode, bit MR1.PMOD has
Sets the QuadLIU
Disables AIS insertion into the data stream (necessary for proper operation)
Sets the receive dual elastic store in a “free running” mode (necessary for proper
operation)
Enables transmit transparent mode (necessary for proper operation)
Sets the transmitter in a “free running” mode (necessary for proper operation)
The QuadLIU
digital line interface. For the analog line interface the codes AMI and HDB3 are
supported. For the digital line interface modes (dual- or single-rail) the QuadLIU
supports AMI, HDB3, CMI (with and without HDB3 precoding).
LOS detection after 176 consecutive “zeros” (fulfills G.775).
LOS recovery after 22 “ones” in the PCD interval. (fulfills G.775).
LOS threshold of 0.6 V (fulfills G.775).
TM
supports requirements for the analog line interface as well as the
TM
into a defined mode (necessary for proper operation)
245
MR1.PMOD = ´0´
XPM(2:0) or TXP(16:1)
GCM(6:1) according to external MCLK clock frequency
CMR(3:1), GPC1; CMR(6:4) and GPC(6:2)
LIM0, LIM1, XPM(2:0)
MR0.XC(1:0), MR0.RC(1:0)
PCD, PCR, LIM1, LIM2
PC(3:1)
Operational Description
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
TM
TM