pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 138

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Field
RLM
LL
MAS
Data Sheet
Bits
2
1
0
Type
rw
rw
rw
Description
Receive Line Monitoring
See
0
1
Local Loop
See
0
1
Master Mode
See also
0
1
B
B
B
B
B
B
Chapter
Chapter
is increased to detect resistively attenuated signals of -20 dB (short-
haul mode only)
receive lines RL1/RL2 or ROID from the receiver. Instead of the
signals coming from the line the data provided by system interface
are routed through the analog receiver back to the system interface.
The unipolar bit stream is transmitted undisturbed on the line.
Receiver and transmitter coding must be identical. Operates in
analog and digital line interface mode. In analog line interface mode
data is transferred through the complete analog receiver.
synchronized to the clock (2.048 MHz or 8 kHz, see IPC.SSYF)
supplied by SYNC. If this pin is connected to VSS or VDD (or left
open and pulled up to VDD internally) the DCO-R circuitry is
centered and no receive jitter attenuation is performed (only if
2.048 MHz clock is selected by resetting bit IPC.SSYF). The
generated clocks are stable.
Normal receiver mode
Receiver mode for receive line monitoring; the receiver sensitivity
Normal operation
Local loop active. The local loop back mode disconnects the
Slave mode
Master mode on. Setting this bit the DCO-R circuitry is frequency
Table
3.7.3.2.
3.11.4.
138
24.
Register DescriptionLine Interface Mode 0
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
TM