pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 83

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

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Note that the configuration of the Bipolar Violation detection by these sequence is reset by a receive reset
(CMDR.RRES = ´1´)
3.7
An overview about the receive path of one channel of the QuadLIU
Figure 22
The recovered clock selection of
The multiplexer “C” in
The multiplexer “D” in
clock or by the DCO-R (see above). The appropriate control register bits are CMR4.RS(2:0) (CMR4). These
register bits selects also different DCO-R output frequencies.
The sources of the receive clock output pins of the QuadLIU
clocks of the channels:
The source of each of the four receive clock pins of the QuadLIU
out of each of the four receive clocks of the channels by programming the registers bits GPC(2:6).RS(2:0) (GPC2),
see cross connection “B” in
Data Sheet
Write ´A7
Write ´00
Receive Line
Interface
SYNC
MCLK
RL1/ROID
RL2
H
Receive Path
Receive System of one Channel
H
´ into REGFP
´ into REGFP
Equalizer
Figure 22
Figure 22
Clocking Unit
Figure
Master
selects if the receive clock RCLK of a channel is sourced by the recovered route
selects the mode of the receive jitter attenuator, see chapter
Figure 22
23.
A: controlled by CMR5.DRSS(2:0)
C: controlled by CMR1.DCS and LIM0.MAS
D: controlled by CMR4.RS(2:0)
J: controlled by CMR2.IRSC and DIC1.RBS(1:0)
Detector
Analog
LOS
(multiplexer “A”) is shown in more detail in
Recovery
Clock &
Data
DPLL
LOS
Detector
Alarm
83
TM
Decoder
clock selection
(RCLK(4:1)), can be selected out of the receive
Recovered
TM
from other
channels
TM
A
(RCLK(4:1)) can be independently selected
is given in
Dual Receive Elastic Buffer
Figure
C
internal
receive
clock
DCO-R
Figure
Functional Description
22.
J
Rev. 1.3, 2006-01-25
Chapter
23.
QLIU _F0117
D
QuadLIU
PEF 22504
FCLKR
RDON
RCLK
RDO
3.7.8.
TM