pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 71

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Figure 12
Every write into or read from a register of the QuadLIU
(micro con roller) and is then confirmed by an acknowledge message ACK from the QuadLIU
configuration automatic acknowledgement is set (bit ACK_EN, see
confirmed, independent on the bit ACK_EN.
The frame structure of this messages are shown in
In general the LSB of every byte is transmitted first and lower bytes are transmitted before higher bytes (regarding
the register address)
Source and destination addresses are 8 bits long. Only the first 6 bits are really used for addressing. The bit C/R
(Command/Response) distinguishes between a command and a response. The bit MS (Master/Slave) is ´0B´ for
all Slaves and ´1B´ for all masters, see
The source address is defined by pinstrapping of A5 to A0 after reset, but other values can be configured by
programming of the SCI configuration register.
The payload of the write CMD includes two control bits (MSBs of the payload), which distinguish between the
different kind of commands, see
CMD payload includes only the control bits and the register address. Register addresses can be either QuadLIU
register addresses or SCI configuration register addresses. Because of the address space of the QuadLIU
really 10 LSBs of the 14 bit address are used in the QuadLIU
The payload of the read ACK includes the content of the register (one byte) in addition to the payload of the write
ACK.
The Frame Check Sequence FCS has 16 bits and is build (or checked) over the address and payload according
to ISO 3309-1984.
The Read Status Byte RSTA of the acknowledge message shows the status of the received message and is built
by the SCI interface of the QuadLIU
The destination address in the ACK message is always the source address of the corresponding CMD (the
address of the micro controller), see
interface
Data Sheet
SCI Message Structure of QuadLIU
HOST
Table
TM
Figure
, see
8, the 14 bit wide register address and the 8 bit wide data whereas the read
Table 9
Figure 15
14, because no CMD messages will be sent by the QuadLIU
CMD
ACK
and
TM
Figure
Figure 13
TM
and
71
is initiated by a command message CMD from the Host
Table
13.
QuadLIU
TM
QLIU_SCI_message_structure
. The 4 MSBs are ignored
7.
Table
9). Read commands are always
Functional Description
Rev. 1.3, 2006-01-25
TM
QuadLIU
PEF 22504
if in the SCI
TM
SCI
TM
TM
TM
,