pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 122

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Interrupt Mask Register 1
Each interrupt source can generate an interrupt signal on port INT (characteristics of the output stage are defined
by register IPC). A “1” in a bit position of IMR(1:4), IMR(6:7) sets the mask active for the interrupt status in ISR(1:4),
ISR(6:7). Masked interrupt statuses neither generate a signal on INT, nor are they visible in register GIS.
Moreover, they are- not displayed in the interrupt status register if bit GCR.VIS is cleared- displayed in the interrupt
status register if bit GCR.VIS is set, see
Note: After reset, all interrupts are disabled.
IMR1
Interrupt Mask Register 1
Field
LLBSC
XLSC
The other Interrupt Mask Registers have the same description.
The Offset Addresses are listed in
Table 37
Register Short Name
IMR2
IMR3
IMR4
IMR6
IMR7
Table 38
bit number
IMR1
Data Sheet
IMRn Overview
Interrupt Mask Registers
7
LLBSC
(E1 only)
Bits
7
1
6
Register Long Name
Interrupt Mask Register 2
Interrupt Mask Register 3
Interrupt Mask Register 4
Interrupt Mask Register 6
Interrupt Mask Register 7
Type
rw
rw
IMRn
5
Description
Interrupt Mask Bit LLBSC
Each interrupt source can generate an interrupt signal on port INT.
Characteristics of the output stage are defined by register IPC. A ´1´ in a
bit position of IMR(7:0) sets the mask active for the interrupt status in the
registers ISR. Mask interrupt statuses neither generate a signal on INT,
not are they visible in register GIS. Moreover they are not displayed in the
interrupt status register if bit GCR.VIS is cleared; they are displayed in the
interrupt status register if bit GCR.VIS is set.
The bit IMR1.LLBSC is only valid in E1 mode. For T1/J1 mode the
equivalent bit is in IMR3.LLBSC.
Interrupt Mask Bit XLSC
Chapter
Overview, for bit names and layout refer to
3.5.3.
4
Offset
xx15
122
H
Register DescriptionInterrupt Mask Register 1
3
2
Offset Address
xx16
xx17
xx18
xx1A
xxDF
H
H
H
H
H
Interrupt Mask
1
XLSC
Rev. 1.3, 2006-01-25
Page Number
QuadLIU
PEF 22504
Reset Value
0
Registers.
FF
TM
H