pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 67

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

3.4
Figure 9
Figure 9
3.5
The four possible micro controller interface modes - two asynchronous modes (Intel, Motorola) and two serial
interface modes (SPI bus or SCI bus) - are selected by using the interface mode selection pins IM(1:0). This
selection is valid immediately after reset becomes inactive.
After changing of the interface mode by IM(1:0), a hardware reset must be applied.
3.5.1
The asychronous micro controller interface is selected if IM(1:0) is strapped to ´00B´ (Intel mode) or ´01B´
(Motorola mode).
An handshake signal (data acknowledge DTACK for Motorola- and READY for Intel-mode) is provided indicating
successful read or write cycle. By using DTACK or READY respectively no counter is necessary in the micro
controller to finish the access, see also timing diagrams
If activated, READY/ DTACK is an open Drain (oD) output and will be only driven to low if CS is low. Therefore the
READY/ DTACK signals of two or more QuadLIU
up resistor (wired or).
The generation of READY /DTACK is asynchronous:
In Intel mode read access READY will be set to low by the QuadLIU
QuadLIU
before it will be set to high by the QuadLIU
Data Sheet
RL1/ROID(1:4)
XL1/XOID(1:4)
RLAS2(1:4)
RL2(1:4)
XL2(1:4)
TM
shows the block diagram of the QuadLIU
. After the rising edge of RD (which is driven by the micro controller), READY is low for a “hold time”,
IM(1:0)
Block Diagram
Block Diagram
Functional Blocks
Asynchronous Micro Controller Interface (Intel or Motorola mode)
Regulator
Voltage
VSEL
TDI,TMS,TCK,TRS,TDO
Analog Switch
Haul Receive
Line Interface
Clock & Data
Haul Transmit
Line Interface
Long+Short
Long+Short
Boundary Scan
Recovery
JTAG
A(9:0)
TM
CS
Asynchronous Micro
Controller Interface
.
WR/RW
Line Decoder
PRBS Monitor
Line Encoder
PRBS Gener.
IBL Generator
IBL Monitor
RD/DS
TM
TM
BHE/BLE
v3.1 can be connect together, using a common external pull-
.
67
ALE
Figure 51
DBW
SCI Interface
RES
Jitter Attunator
Receive
INT
Dual Receive
Elastic Buffer
Dual Transmit
Elastic Buffer
ff.
READY/TDACK
READY_EN
Jitter Attunator
Transmit
SPI Interface
TM
after the data output is stable at the
D(15:0)
MUX
MUX
MCLK SYNC FSC
Interface
Transmit
Interface
Receive
Framer
Framer
Master Clocking
Functional Description
Unit
TCLK
RCLK
Rev. 1.3, 2006-01-25
QLIU_blockdiagram
QuadLIU
PEF 22504
FCLKR(1:4)
RDO(1:4)
RPA(1:4)
RPB(1:4)
RPC(1:4)
RPD(1:4)
XDI(1:4)
XPA(1:4)
XPB(1:4)
XPC(1:4)
XPD(1:4)
FCLKX(1:4)
TM