pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 95

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 24
Mode
Master
Master
Master
Slave
Slave
Slave
Slave
The receive clock output RCLK of every channel can be switched between 2 sources, see multiplexer “D” in
Figure
•
•
3.7.8.1
For E1 the jitter attenuator meets the jitter transfer requirements of the ITU-T I.431 and G.735 to 739 (refer to
Figure
For T1/J1 the jitter attenuator meets the jitter transfer requirements of the PUB 62411, PUB 43802, TR-
TSY 009,TR-TSY 253, TR-TSY 499 and ITU-T I.431 and G.703 (refer to
Data Sheet
If the DCO-R is the source of RCLK the following frequencies are possible: 1.544, 3.088, 6.176, and 12.352 in
T1/J1 mode and 2.048, 4.096, 8.192, and 16.384 MHz in E1 mode. Controlling of the frequency is done by the
register bits CMR4.RS(1:0).
If the recovered clock out (of the clock and data recovery) is the source of RCLK (see multiplexer “D” in
Figure
22:
30)
22), only 2.048 MHz (1.544 MHz) is possible as output frequency.
Clocking Modes of DCO-R
Receive Jitter Attenuation Performance
Internal LOS
Active
Independent
Independent
Independent
No
No
Yes
Yes
SYNC Input
Fixed to
2.048 MHz
(E1) or
1.544 MHz
(T1)
8.0 kHz
Fixed to
2.048 MHz
(E1) or
1.544 MHz
(T1)
Fixed to
2.048 MHz
V
V
V
DD
DD
DD
System Clocks generated by DCO-R
DCO-R centered, if CMR2.DCF = ´0´. (CMR2.DCF should not be
set), see also
Synchronized to SYNC input (external 2.048 MHz or 1.544 MHz,
IPC.SSYF = ´0´), see also
Synchronized to SYNC input (external 8.0 kHz, IPC.SSYF = ´1´,
CMR2.DCF = ´0´)
Synchronized to recovered line clock
Synchronized to recovered line clock
CMR1.DCS = ´0´: DCO-R is centered, if CMR2.DCF = ´0´.
(CMR2.DCF should not be set)
CMR1.DCS = ´1´: Synchronized on recovered line clock
CMR1.DCS = ´0´: Synchronized to SYNC input
(external 2.048 MHz or 1.544 MHz)
CMR1.DCS = ´1´: Synchronized on recovered line clock
95
CMR2
Figure
IPC
31).
Functional Description
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
TM