pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 59

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
32
33
34
35
120
121
122
123
120
121
122
123
120
121
122
123
120
121
122
123
Data Sheet
Name
RPA4
RPB4
RPC4
RPD4
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
I/O
I/O
I
I
I
Buffer
Type
PU/–
PU/–
PU
PU
PU
Function
Receive Multifunction Pins A to D, port 4
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIU
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions as described for port 1.
Transmit Multifunction Pins A to D, port 1
Depending on programming of bits PC(1:4).XPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIU
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESX latching/transmission of data is done with the
rising or falling edge of SCLKX. If not connected, an internal
pullup transistor ensures a high input level.
Each input function (SYPX, XMFS, XSIG,TCLK, XLT or XLT)
may only be selected once. SYPX and XMFS must not be
used in parallel.
Selectable pin functions are described below.
Synchronous Pulse Transmit, port 1
SYPX, PC(1:4).XPC(3:0) = ´0000
Together with the values of registers XC(0:1) this signal
defines the beginning of time slot 0 at system highway port
XDI.
The pulse cycle is an integer multiple of 125 s.
SYPX must not be used in parallel with XMFS.
Tran4mit Multiframe Synchronization (XMFS), port 1
PC(1:4).XPC(3:0) = 0001
This port defines the frame and multiframe begin on the
transmit system interface ports XDI and XSIG.
Depending on PC5.CXMFS the signal on XMFS is active
high or low.
XMFS must not be used in parallel with SYPX.
Note: A new multiframe position has settled at least one
Transmit Signaling Data (XSIG), port 1
PC(1:4).XPC(3:0) = 0010
Input for transmit signaling data received from the signaling
highway. Optionally, (SIC3.TTRF = 1), sampling of XSIG
data is controlled by the active high XSIGM marker. At higher
data rates sampling of data is defined by bits
SIC2.SICS(2:0).
59
multiframe after pulse XMFS has been supplied.
B
B
B
TM
´
TM
. After reset these ports
. After reset the ports
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM