pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 143

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Loop Code Register 1
LCR1
Loop Code Register 1
Field
EPRM
XPRBS
LDC
LAC
FLLB
LLBP
Data Sheet
Bits
7
6
5:4
3:2
1
0
Type
rw
rw
rw
rw
rw
rw
Description
Enable Pseudo-Random Binary Sequence Monitor
See
0
1
Transmit Pseudo-Random Binary Sequence
A one in this bit position enables transmission of a pseudo-random binary
sequence to the remote end. Depending on bit LLBP the PRBS is
generated according to 2
restriction (ITU-T O. 151). See
Length Deactivate (Down) Code
These bits defines the length of the LLB deactivate code which is
programmable in register LCR2.
00
01
10
11
Length Activate (Up) Code
These bits defines the length of the LLB activate code which is
programmable in register LCR3.
00
01
10
11
Framed Line Loop-Back/Invert PRBS
Depending on bit LCR1.XPRBS this bit enables different functions:
LCR1.XPRBS = ´0´:
Note: Invert PRBS LCR1.XPRBS = ´1´: see
Line Loop-Back Pattern
See
LCR1.XPRBS = ´0´: see
LCR1.XPRBS = ´1´ or LCR1.EPRM = ´1´: see
B
B
B
B
B
B
B
B
B
B
Chapter
Chapter 3.11.2
error counter with each detected PRBS bit error. With any change
of state of the PRBS internal synchronization status an interrupt
ISR1.LLBSC is generated. The current status of the PRBS
synchronizer is indicated by bit LSR2.LLBAD.
Pseudo-Random Binary Sequence (PRBS) monitor is disabled.
PRBS is enabled. Setting this bit enables incrementing the CEC2
Length: 5 bit
Length: 6 bit, 2 bit, 3 bit
Length: 7 bit
Length: 8 bit, 2 bit, 4bit
Length: 5 bit
Length: 6 bit, 2 bit, 3 bit
Length: 7 bit
Length: 8 bit, 2 bit, 4 bit
Offset
xx3B
3.11.1.
143
H
Table
Table 43
15
41.
Register DescriptionLoop Code Register 1
-1 or 2
Chapter
20
-1 with a maximum-14-zero
3.11.1.
Table 42
Table 44
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H