pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 28

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
N6
D10, D7, L5, N9
Digital (Framer) Interface Receive
E1
E2
F1
F3
K1
J4
K4
L1
Digital (Framer) Interface Transmit
B3
C3
H3
G3
H1
Data Sheet
L10
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
SYNC
FSC
RCLK(1:4)
RDO1
FCLKR1
RDO2
FCLKR2
RDO3
FCLKR3
RDO4
FCLKR4
XDI1
FCLKX1
XDI2
FCLKX2
XDI3
Pin Type Buffer
I
O
O
O
I/O
O
I/O
O
I/O
O
I/O
I
I/O
I
I/O
I
Type
PU
–
–
–
PU
–
PU
–
PU
–
PU
–
–
–
–
–
28
Function
Clock Synchronization of DCO-R
If a clock is detected on pin SYNC the
DCO-R circuitry of the QuadLIU
1.544/2.048 MHz clock (see LIM0.MAS, CMR1.DCS
and CMR2.DCF). Additionally, in master mode the
QuadLIU
clock (IPC.SSYF = ´1´). If not connected, an internal
pull-up transistor ensures high input level.
8 kHz Frame Synchronization
The optionally synchronization pulse is active high or
low for one 2.048/1.544 MHz cycle (pulse width =
488 ns for E1and 648 ns or T1/J1).
Receive Clock Out, ports 1 to 4
After reset this ports are configured to be internally
pulled up weakly. Setting of register bit PC5.CRPR will
switch this ports to be active outputs.
Receive Data Out, port 1
Received data at RL1, RL2 is sent to RDOP, RDON.
Clocking of data is done with the rising or falling edge of
RCLK.
Framer Data Clock Receive, port 1
Input if PC5.CSRP = ´0´, output if PC5.CSRP = ´1´.
Receive Data Out, port 2
See description of RDOP1.
Framer Data Clock Receive, port 2
See description of FCLKR1.
Receive Data Out, port 3
See description of RDOP1.
Framer Data Clock Receive, port 3
See description of FCLKR1.
Receive Data Out, port 4
See description of RDOP1.
Framer Data Clock Receive, port 4
See description of FCLKR1.
Transmit Data In, port 1
NRZ transmit data received from the framer. Latching of
data is done with rising or falling transitions of FCLKX1
according to bit DIC3.RESX.
Framer Data Clock Transmit, port 1
Transmit Data In, port 2
See description of XDI1.
Framer Data Clock Transmit, port 2
See description of FCLKX1.
Transmit Data In, port 3
See description of XDI1.
TM
is able to synchronize to an 8 kHz reference
TM
Rev. 1.3, 2006-01-25
synchronizes to this
Pin Descriptions
QuadLIU
PEF 22504
TM