pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 168

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Global Clock Mode Register 2
GCM2
Global Clock Mode Register 2
Field
PHSDEM
PHSDIR
PHSDS
VFREQ_EN
Data Sheet
Bits
7
6
5
4
Type
rw
rw
rw
rw
Description
RX Phase Decoder Demand
0
1
RX Phase Decoder Direction
0
1
RX Phase Decoder Switch
0
1
Variable Frequency Enable
If “fixed mode” mode is selected the clock frequency at the pin MCLK
must be 2.048 for E1 or 1.544 MHz for T1/J1 respectively. The setting of
the whole clock mode is done automatically: Register bits of GCM1,
GCM2.PHSDEM, PHDIR, PHSDS, PHD_E1 and GCM3 to GCM8 are
unused. If “fixed mode” mode is selected and the SPI- or SCI-interface is
used as controller interface, the pinstrapping values at D(15:5) are also
not used. See also
Note: If “fixed mode “ is enabled all of the four ports must work in the same
0
1
B
B
B
B
B
B
B
B
mode, either in T1 or in E1 mode. A switching between E1 and T1
modes causes a reset of the whole clock system. If “fixed mode“ is
disabled a switching between E1 and T1 mode (which can be done
in this case individually for every port) causes not a reset of the
whole clock system.
reset)
Variable master clock frequency (normal operation, operation after
default operation
see formulas in GCM6.
default operation
see formulas in GCM6.
default operation
see formulas in GCM6.
Fixed clock frequency of 2.048 (E1) or 1.544 MHz (T1/J1)
Offset
0093
168
H
Register DescriptionGlobal Clock Mode Register 2
Chapter
3.5.5.
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
10
TM
H