pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 51

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
70
Clock Signals
133
48
Data Sheet
Name
XL2.4
XDON4
XFM4
MCLK
SYNC
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
O (analog) –
O
O
I
I
Buffer
Type
–
–
–
PU
Function
Transmit Line 2, port 4
Analog output for the external transformer. Selected if
LIM1.DRS is cleared. After reset this pin is in high-
impedance state until bit FMR0.XC1 is set and XPM2.XLT is
cleared.
Transmit Data Output Negative, port 4
This digital output for transmitted dual-rail
PCM(-) route signals can provide
•
•
The data is clocked on positive transitions of XCLK4 in both
cases. Output polarity is selected by bit LIM0.XDOS (after
reset: active low).
The dual-rail mode is selected if LIM1.DRS and FMR0.XC1
are set. After reset this pin is in high-impedance state until
register LIM1.DRS is set and XPM2.XLT cleared.
Transmit Frame Marker, port 4
This digital output marks the first bit of every frame
transmitted on port XDOP. This function is only available in
the optical interface mode (LIM1.DRS = 1
0
reset this pin is in high-impedance state until register
LIM1.DRS is set and XPM2.XLT cleared.
In remote loop configuration the XFM4 marker is not valid.
Master Clock
A reference clock of better than ±32 ppm accuracy in the
range of 1.02 to 20 MHz must be provided on this pin. The
QuadLIU
master
(see registers GCM(8:1)).
Clock Synchronization of DCO-R
If a clock is detected on pin SYNC the
DCO-R circuitry of the OctalFALCTM synchronizes to this
1.544/2.048 MHz clock (see LIM0.MAS, CMR1.DCS and
CMR2.DCF). Additionally, in master mode the OctalFALCTM
is able to synchronize to an 8 kHz reference clock (IPC.SSYF
= 1
high input level.
B
). Data is clocked on positive transitions of XCLK4. After
B
51
Half bauded signals with 50% duty cycle (LIM0.XFB = 0
or
Full bauded signals with 100% duty cycle (LIM0.XFB =
1
). If not connected, an internal pullup transistor ensures
B
)
TM
internally derives all necessary clocks from this
Rev. 1.3, 2006-01-25
B
and FMR0.XC1 =
Pin Descriptions
QuadLIU
PEF 22504
TM
B
)