pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 31

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
L3
L2
M3
N3
B9
B11
C9
D9
B9
B11
C9
D9
B9
B11
C9
D9
B9
B11
C9
D9
Data Sheet
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
RPA4
RPB4
RPC4
RPD4
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
XPA1
XPB1
XPC1
XPD1
Pin Type Buffer
I/O
I/O
I
O
I
Type
PU/–
PU/–
PU
–
PU
31
Function
Receive Multifunction Pins A to D, port 4
Depending on programming of bits PC(1:4).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIU
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions as described for port 1.
Transmit Multifunction Pins A to D, port 1
Depending on programming of bits PC(1:4).XPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIU
reset the ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESX
latching/transmission of data is done with the rising or
falling edge of FCLKX. If not connected, an internal pull-
up transistor ensures a high input level.
Each input function (TCLK, XDIN, XLT or XLT) may only
be selected once.
Selectable pin functions are described below.
Transmit Clock (TCLK), port 1
PC(1:4).XPC(3:0) = ´0011
A 2.048/8.192 MHz (E1) or 1.544/6.176 MHz (T1/J1)
clock has to be sourced by the framer if the internally
generated transmit clock (generated by DCO-X) shall
not be used. Optionally this input is used as a
synchronization clock for the DCO-X circuitry with a
frequency of 2.048 (E1) or 1.544 MHz (T1/J1).
Transmit Clock (XCLK), port 1
PC(1:4).XPC(3:0) = ´0111
Transmit line clock of 2.048 MHz (E1) or 1.544 MHz
(T1/J1) derived from FCLKX/R, RCLK or generated
internally by DCO circuitries.
Transmit Line Tristate (XLT), port 1
PC(1:4).XPC(3:0) = ´1000
A high level on this port sets the transmit lines XL1/2 or
XDOP/N into tristate mode. This pin function is logically
OR´d with register bit XPM2.XLT.
b
b
b
´
´
´
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM
TM
. After
. After
TM