pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 173

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Global Clock Mode Register 6
Note: Write operations to GCM5 and GCM6 initiate a PLL reset if the asynchronous interface is selected (IM(1:0)
GCM6
Global Clock Mode Register 6
Field
PLL_N
Flexible Clock Mode Settings:
If “flexible master clock mode” is used (VFREQ_EN = ´1´), the according register settings can be calculated as
follows (a windows-based program for automatic calculation is available, see
standard frequencies see the table below.
1. The master clock MCLK must be in the following frequency range:
1.02 MHz
2. Generally the PLL of the master clocking unit includes an input divider with a dividing factor PLL_M +1 and a
feedback divider with a dividing factor 4 x (PLL_N +1). So it generates a clock
f
3. The selection of PLL_N and PLL_M must be done in the following way:
The PLL frequency
200 MHz
The combinations of the values PLL_M and PLL_M must fulfill the equations:
2 MHz
5 MHz
4. In E1 mode, the selection of PHSN_E1 and PHSX_E1 must be done in such a manner that the frequency for
the receiver
f
In T1/J1 mode, the selection of PHSN_T1 and PHSX_T1 must be done in such a manner that the frequency for
the receiver
f
GCM2.PHSDEM, GCM2.PHSDIR, GCM2.PHSDS, PC5.PHDSX and PC5.PHDSR must be left to ´0´
Data Sheet
PLL
RX_E1
RX_T1
=
= ´0x´) and if the “flexible master clocking mode” is selected (GCM2.VFREQ_EN = ´1´), see
f
=
=
MCLK
f
f
PLL
PLL
f
f
MCLK
MCLK
f
x 4 x (PLL_N +1) / (PLL_M +1).
f
/ {PHSN_E1 + (PHSX_E1 / 6)}.
/ {PHSN_T1 + (PHSX_T1 / 6)}.
PLL
f
f
MCLK
RX_E1
RX_T1
/ (PLL_M +1)
/ (PLL_M +1)
Bits
4:0
300 MHz.
has nearly the value 16 x
has nearly the value 16 x
20 MHz
f
PLL
must be in the following range:
Type
rw
6 MHz , if PLL_N is in the range 25 to 63.
15 MHz , if PLL_N is in the range 1 to 24.
Description
PLL Dividing Factor N
For details see calculation formulas below and
000001
...
111111
B
f
f
DATA_E1
DATA_T1
B
B
1
63
x (1 + 100ppm) = 24.706 MHz:
x (1 + 100ppm) = 32.7713 MHz:
Offset
0097
173
H
Register DescriptionGlobal Clock Mode Register 6
f
PLL
Chapter
of about
Table
8.3. For some of the
Rev. 1.3, 2006-01-25
49.
Chapter
QuadLIU
PEF 22504
Reset Value
3.5.5.1.
00
TM
H