pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 197

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Line Status Register 0
LSR0
Line Status Register 0
Field
LOS
AIS
Data Sheet
Bits
7
6
Type
r
r
Description
Loss-of-Signal
•
•
Alarm Indication Signal
The function of this bit is determined by MR0.ALM.
•
•
The bit is also set during alarm simulation and reset if MR0.SIM is cleared
and no alarm condition exists.With the rising edge of this bit an interrupt
status bit (ISR2.AIS) is set.
Detection: This bit is set when the incoming signal has “no transitions”
(analog interface) or logical zeros (digital interface) in a time interval
of T consecutive pulses, where T is programmable by register PCD.
Total account of consecutive pulses: 16 T 4096. Analog interface:
The receive signal level where “no transition” is declared is defined by
the programmed value of LIM1.RIL(2:0).
Recovery: Analog interface: The bit is reset in short-haul mode when
the incoming signal has transitions with signal levels greater than the
programmed receive input level (LIM1.RIL(2:0)) for at least M pulse
periods defined by register PCR in the PCD time interval. In long-haul
mode additionally bit RES.6 must be set for at least 250 s. Digital
interface: The bit is reset when the incoming data stream contains at
least M ones defined by register PCR in the PCD time interval. With
the rising edge of this bit an interrupt status bit (ISR2.LOS) is set. The
bit is also set during alarm simulation and reset, if MR0.SIM is cleared
and no alarm condition exists.
MR0.ALM = ´0´: This bit is set when two or less zeros in the received
bit stream are detected in a time interval of 250 ms and the
QuadLIU
when no alarm condition is detected (according to ETSI standard).
MR0.ALM = ´1´: This bit is set when the incoming signal has two or
less Zeros in each of two consecutive double frame period (512 bits).
This bit is cleared when each of two consecutive doubleframe periods
contain three or more zeros or when the frame alignment signal FAS
has been found. (ITU-T G.775)
TM
Offset
xx4C
197
is in asynchronous state (LSR0.LFA = ´1´). The bit is reset
H
Register DescriptionLine Status Register 0
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H