pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 102

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

3.9
The transmit path of the QuadLIU
Figure 36
The serial transmit bit stream (single rail or dual rail) is processed by the transmitter which has the following
functions:
•
•
3.9.1
The transmit line interface includes two integrated serial resistors R
modes are possible:
•
•
In E1 mode the value of R
Note that shorts between XL1 and XL2 cannot be detected, because the short circuit current is lower than 120 mA.
This way a short between XL1 and XL2 will not harm the device
The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return to zero signals of the
appropriate programmable shape. The unipolar data is provided on pin XDI and the digital transmitter.
Data Sheet
Transmit Line
Interface
XL1/XOID
AIS generation (blue alarm)
Generation of In-band loop-up/-down code
For non-generic applications the extermal serial resistance R
(E1/T1/J1) as shown in
For generic E1/T1/J1 applications with optimized return loss the transmit output resistance R
by the register bit PC6.TSRE: The operation mode (E1/T1/J1) is selected by software without the need for
external hardware changes: Here the external resistor R
MCLK
XCLK
XL3
XL2
XL4
Transmit Path
Transmit System of one Channel
Transmit Line Interface
E: controlled by CMR2.IXSC and CMR2.IRSC
F: controlled by CMR1.DXSS and automatic transmit clock switching
G: controlled by LIM1.RL,JATT and LIM2.ELT
H: controlled by DIC1.XBS(1:0) and automatic transmit clock switching
%: divider: controlled by CMR6.STF(2:0)
Clocking Unit
Master
SER
Table
in
Table 28
DAC
TM
28. The additional register bit PC6.TSRE is not used, R
is shown in
Shaper,
Pulse
LBO
is valid for both characteristic line impedances Z
Figure
102
36.
Encoder
SER
is always 0 , see
H
SER
TX
as shown in
Dual Transmit Elastic Buffer
is dependent on the operation mode
DCO-X
Automatic Transmit
Clock Switching
recovered
receive clock
Table
G
Figure
Functional Description
0
28.
TX
= 120
F
internal
transmit
clock
Rev. 1.3, 2006-01-25
is always 2
37. Two application
QLIU _ITS 10305
TX
%
E
and Z
QuadLIU
PEF 22504
from
DCO-R
is configured
0
XDIP
XDIN
FCLKR
FCLKX
TCLK
(in)
= 75 .
TM