pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 30

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 1
Pin No.
D2
D3
D1
D4
D2
D3
D1
D4
F4
G2
G1
G4
H4
J1
J3
J2
Data Sheet
I/O Signals (cont’d)for P/PG-LBGA-160-1
Name
RPA1
RPB1
RPC1
RPD1
RPA1
RPB1
RPC1
RPD1
RPA2
RPB2
RPC2
RPD2
RPA3
RPB3
RPC3
RPD3
Pin Type Buffer
O
O
I/O
I/O
Type
–
–
PU/–
PU/–
30
Function
Receive Data Output Negative (RDON), port 1
PC(1:4).RPC(3:0) = ´1110
Receive data output negative for dual rail mode on
digital (framer) interface (LIM3.DRR = ´1´).
Bipolar violation output for single rail mode on digital
(framer) interface (LIM3.DRR = ´0´).
Receive Clock Output (RCLK), port 1
PC(1:4).RPC(3:0) = ´1111
Receive clock output RCLK. After reset RCLK is
configured to be internally pulled up weekly. By setting
of PC5.CRP RCLK is an active output.
RCLK source and frequency selection is made by
CMR1.RS(1:0) if COMP = ´1´ or by CMR4.RS(2:0) if
COMP = ´0´.
Receive Multifunction Pins A to D, port 2
Depending on programming of bits PC(1:4).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIU
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions as described for port 1.
Receive Multifunction Pins A to D, port 3
Depending on programming of bits PC(1:4).RPC(3:0)
these multifunction ports carry information to the framer
interface or from the framer to the QuadLIU
reset these ports are configured to be inputs. With the
selection of the appropriate pin function, the
corresponding input/output configuration is achieved
automatically. Depending on bit DIC3.RESR
latching/transmission of data is done with the rising or
falling edge of FCLKR. If not connected, an internal pull-
up transistor ensures a high input level.
An input function must not be selected twice or more.
Selectable pin functions as described for port 1.
b
b
´.
´. Default setting after reset
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
TM
TM
. After
. After
TM