pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 55

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Table 2
Pin No.
20
21
49
50
Multi Function Pins
4
5
6
7
Data Sheet
Name
XDI3
SCLKX3
XDI4
SCLKX4
RPA1
RPB1
RPC1
RPD1
I/O Signals for P-TQFP-144-8 (cont’d)
Pin Type
I
I
I
I
I/O
Buffer
Type
–
PU
–
PU
PU/–
Function
Transmit Data In, port 3
Transmit data received from the system highway. Latching of
data is done with rising or falling transitions of SCLKX3
according to bit SIC3.RESX.
The delay between the beginning of time slot 0 and the initial
edge of SCLKX3 (after SYPX goes active) is determined by
the registers XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data rates sampling
of data is defined by bits SIC2.SICS(2:0).
System Clock Transmit, port 3
Working clock for the transmit system interface with a
frequency of 16.384/8.192/4.096/2.048 in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1
mode.
Transmit Data In, port 4
Transmit data received from the system highway. Latching of
data is done with rising or falling transitions of SCLKX4
according to bit SIC3.RESX.
The delay between the beginning of time slot 0 and the initial
edge of SCLKX4 (after SYPX goes active) is determined by
the registers XC(1:0).
In higher (more than 1.544/2.048 Mbit/s) data rates sampling
of data is defined by bits SIC2.SICS(2:0).
System Clock Transmit, port 4
Working clock for the transmit system interface with a
frequency of 16.384/8.192/4.096/2.048 in E1 mode and
16.384/8.192/4.096/2.048 MHz (SIC2.SSC2 = 0
12.352/6.176/3.088/1.544 MHz (SIC2.SSC2 = 1
mode.
Receive Multifunction Pins A to D, port 1
Depending on programming of bits PC(1:4).RPC(3:0) these
multifunction ports carry information to the system interface
or from the system to the QuadLIU
are configured to be inputs. With the selection of the
appropriate pin function, the corresponding input/output
configuration is achieved automatically. Depending on bit
SIC3.RESR latching/transmission of data is done with the
rising or falling edge of SCLKR. If not connected, an internal
pullup transistor ensures a high input level.
The input function must not be selected twice or more.
Selectable pin functions are described below.
55
TM
. After reset these ports
Rev. 1.3, 2006-01-25
Pin Descriptions
QuadLIU
PEF 22504
B
B
B
B
) or
) in T1/J1
) or
) in T1/J1
TM