pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 208

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Interrupt Status Register 2
All bits are reset when ISR2 is read. If bit GCR.VIS is set, interrupt statuses in ISR2 are flagged although they are
masked by register IMR2. However, these masked interrupt statuses neither generate a signal on INT, nor are
visible in register GIS. See
ISR2
Interrupt Status Register 2
Field
AIS
LOS
Data Sheet
Bits
3
2
Chapter 3.5.3
Type
r
r
Description
Alarm Indication Signal (Blue Alarm)
This bit is set when an alarm indication signal is detected and bit
LSR0.AIS is set. If GCR.SCI is set high this interrupt status bit is activated
with every change of state of LSR0.AIS.It is set during alarm simulation.
Loss-of-Signal (Red Alarm)
This bit is set when a loss-of-signal alarm is detected in the received data
stream and LSR0.LOS is set. If GCR.SCI is set high this interrupt status
bit is activated with every change of state of LSR0.LOS. It is set during
alarm simulation.
Offset
xx6A
208
H
Register DescriptionInterrupt Status Register 2
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
00
TM
H