pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 172

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Global Clock Mode Register 5
Note: Write operations to GCM5 and GCM6 initiate a PLL reset if the asynchronous interface is selected (IM(1:0)
GCM5
Global Clock Mode Register 5
Field
MCLK_LOW
PLL_M
Data Sheet
= ´0x´) and if the “flexible master clocking mode” is selected (GCM2.VFREQ_EN = ´1´), see
Bits
7
4:0
Type
rw
rw
Description
Master Clock Range Low
This bit can be write and read to be software compatible to QuadLIU, but
has no influence on the clock system.
PLL Dividing Factor M
For details see calculation formulas in register
00001
...
11111
B
B
B
1
31
Offset
0096
172
H
Register DescriptionGlobal Clock Mode Register 5
GCM6
Rev. 1.3, 2006-01-25
and
Chapter
Table
QuadLIU
PEF 22504
Reset Value
49.
3.5.5.
00
TM
H