pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 202

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Line Status Register 2
LSR2
Line Status Register 2
Field
LLBDD
LLBAD
Data Sheet
Bits
4
3
Type
r
r
Description
Line Loop-Back Deactivation Signal Detected
Only valid in E1 mode
In T1/J1 mode the equivalent bit is LSR1.LLBDD.
This bit is set in case of the LLB deactivate signal is detected and then
received over a period of more than 25 ms with a bit error rate less than
10
If framing is aligned, the time slot 0 is not taken into account for the error
rate calculation.Any change of this bit causes an LLBSC interrupt.
Line Loop-Back Activation Signal Detected
Only valid in E1 mode
In T1/J1 mode the equivalent bit is LSR1.LLBAD.
Depending on bit LCR1.EPRM the source of this status bit changed.
•
•
-2
LCR1.EPRM = ´0´: This bit is set in case of the LLB activate signal is
detected and then received over a period of more than 25 ms with a
bit error rate less than 10
rate does not exceed 10
taken into account for the error rate calculation. Any change of this bit
causes an LLBSC interrupt.
LCR1.EPRM = ´1´: The current status of the PRBS synchronizer is
indicated in this bit. It is set high if the synchronous state is reached
even in the presence of a bit error rate of 10
containing all zeros or all ones with/without framing bits is also a valid
pseudo-random binary sequence.
. The bit remains set as long as the bit error rate does not exceed 10
Offset
xx4F
202
H
Register DescriptionLine Status Register 2
-2
-2
. If framing is aligned, the time slot 0 is not
. The bit remains set as long as the bit error
-1
. A data stream
Rev. 1.3, 2006-01-25
QuadLIU
PEF 22504
Reset Value
xx
TM
-2
H
.