pef22504 Infineon Technologies Corporation, pef22504 Datasheet - Page 200

• Manufacturer Part Number: pef22504
• Description: Quad E1/t1/j1 Line Interface Component For Long- And Short-haul Applications Pef 22504 E, Pef 22504 Ht, Version 2.1
• Manufacturer: Infineon Technologies Corporation

Line Status Register 3
LSR3
Line Status Register 3
Field
ESC
Table 53
Tested Alarms ESC(2:0) =
LFA
LMFA
RRA (bit2 = 0)
RRA (S-bit frame 12)
RRA (DL-pattern)
LOS
EBC
EBC
AIS
FEC
CVC
CEC (only ESF)
RSP
RSN
XSP
XSN
BEC
COEC
1) Only active during FMR0.SIM = 1
2) FEC is counting +2 while EBC is counting +1 if the framer is in synchronous state; if asynchronous in state 2 but
Data Sheet
synchronous in state 6, counters are incremented during state 6
1)
1)
2)
2)
2)
1)
(F12,F72)
(only ESF)
Alarm Simulation States
Bits
7:5
Type
r
Description
Error Simulation Counter, T1 only
This three-bit counter is incremented by setting bit MR0.SIM. The state of
the counter determines the function to be tested. For complete checking
of the alarm indications, eight simulation steps are necessary (LSR3.ESC
= ´000
b
´ after a complete simulation).
0
Offset
xx4E
200
x
x
x
x
x
x
x
x
x
H
1
x
x
x
x
x
x
x
x
x
x
x
x
Register DescriptionLine Status Register 3
2
3
4
x
x
x
x
x
x
x
x
Rev. 1.3, 2006-01-25
5
x
x
x
(x)
(x)
x
(x)
x
x
QuadLIU
PEF 22504
Reset Value
6
7
xx
TM
H